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1. 发明申请

US20060163635A1 CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS 失效
标题翻译： SOI CMOS技术的BIOI氧化物电容器防止软错误
公开(公告)号：US20060163635A1
公开(公告)日：2006-07-27
申请号：US10905906
申请日：2005-01-26
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

2. 发明申请

US20050184720A1 Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
标题翻译：电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性
公开(公告)号：US20050184720A1
公开(公告)日：2005-08-25
申请号：US11088953
申请日：2005-03-24
申请人： Kerry Bernstein , Ronald Bolam , Edward Nowak , Alvin Strong , Jody Van Horn , Ernest Wu
发明人： Kerry Bernstein , Ronald Bolam , Edward Nowak , Alvin Strong , Jody Van Horn , Ernest Wu
IPC分类号： G01N27/00 , G01R27/00 , G01R31/02 , G01R31/28
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译：一种用于预测门可靠性的方法和系统。该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分失败，确定第一个失败与第二个失败之间的关系，第n个失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。这种关系可以量化。

3. 发明申请

US20070272961A1 CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS 有权
标题翻译： SOI CMOS技术的BIOI氧化物电容器防止软错误
公开(公告)号：US20070272961A1
公开(公告)日：2007-11-29
申请号：US11838931
申请日：2007-08-15
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

4. 发明申请

US20070195841A1 CHARGE NEUTRALIZATION IN SEMICONDUCTOR STRUCTURES 失效
标题翻译：半导体结构中的电荷中和
公开(公告)号：US20070195841A1
公开(公告)日：2007-08-23
申请号：US11276248
申请日：2006-02-21
申请人： John Aitken , Ethan Cannon , Alvin Strong
发明人： John Aitken , Ethan Cannon , Alvin Strong
IPC分类号： H01S5/00
CPC分类号： H01L21/743 , H01L21/76275
摘要： A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.
摘要翻译：一种用于中和掩埋氧化物层中的俘获电荷的方法。该方法包括提供半导体结构，该半导体结构包括（a）半导体层，（b）半导体层顶部的电荷累积层，和（c）与该半导体层直接物理接触的掺杂区域，其中电荷累积层包括第一符号的俘获电荷，并且其中所述掺杂区域和所述半导体层形成PN结二极管。接下来，在P-N结二极管中产生自由电荷，其中自由电荷是与第一符号相反的第二符号。接下来，免费电荷朝向电荷累积层加速，导致一些自由电荷进入电荷累积层并中和电荷累积层中的一些俘获电荷。

5. 发明申请

US20060103007A1 HEATER FOR ANNEALING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 失效
标题翻译：用于在半导体器件中退火捕获电荷的加热器
公开(公告)号：US20060103007A1
公开(公告)日：2006-05-18
申请号：US10904483
申请日：2004-11-12
申请人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
发明人： John Aitken , Ethan Cannon , Philip Oldiges , Alvin Strong
IPC分类号： H01L21/48 , H01L23/34
CPC分类号： H01L24/80 , H01L23/345 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/00
摘要： A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.
摘要翻译：一种从半导体器件退火俘获电荷的结构和相关方法。半导体结构包括基板和第一加热元件。衬底包括体层，绝缘体层和器件层。第一加热元件形成在本体层内。第一加热元件的第一侧与绝缘体层的第一部分相邻。第一加热元件适于被选择性地激活以产生热能来加热绝缘体层的第一部分并且从绝缘体层的第一部分退火被俘获的电荷。

6. 发明申请

US20060226142A1 Enhancement of performance of a conductive wire in a multilayered substrate 失效
公开(公告)号：US20060226142A1
公开(公告)日：2006-10-12
申请号：US11442911
申请日：2006-05-30
申请人： Jason Gill , David Harmon , Deborah Massey , Alvin Strong , Timothy Sullivan , Junichi Furukawa
发明人： Jason Gill , David Harmon , Deborah Massey , Alvin Strong , Timothy Sullivan , Junichi Furukawa
IPC分类号： H05B1/02
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

7. 发明申请

US20060163685A1 THERMO-MECHANICAL CLEAVABLE STRUCTURE 有权
标题翻译：热机械可靠结构
公开(公告)号：US20060163685A1
公开(公告)日：2006-07-27
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn Christiansen , Richard Kontra , Tom Lee , Alvin Strong , Timothy Sullivan , Joseph Therrien
发明人： Fen Chen , Cathryn Christiansen , Richard Kontra , Tom Lee , Alvin Strong , Timothy Sullivan , Joseph Therrien
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

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