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71. 发明授权

US07229876B2 Method of fabricating memory 有权
标题翻译：制造记忆的方法
公开(公告)号：US07229876B2
公开(公告)日：2007-06-12
申请号：US11138612
申请日：2005-05-25
申请人： Kent Kuohua Chang , Jongoh Kim , Yider Wu
发明人： Kent Kuohua Chang , Jongoh Kim , Yider Wu
IPC分类号： H01L21/8244
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
摘要翻译：描述了一种制造存储器件的方法。在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

72. 发明授权

US07067388B1 Flash memory device and method of forming the same with improved gate breakdown and endurance 失效
标题翻译：闪存器件及其形成方法具有改进的栅极击穿和耐久性
公开(公告)号：US07067388B1
公开(公告)日：2006-06-27
申请号：US10819162
申请日：2004-04-07
申请人： Angela Hui , Yider Wu
发明人： Angela Hui , Yider Wu
IPC分类号： H04L29/02
CPC分类号： H01L21/28273 , H01L29/7881
摘要： The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.
摘要翻译：本发明提供了一种闪存器件及其制造方法，其具有在衬底中形成的具有半导体衬底和浅沟槽隔离（STI）结构的浮动栅极结构。在衬底和STI结构上形成第一多晶硅层。形成在第一多晶硅层内的凹槽在STI结构之上并且延伸穿过第一多晶硅层到STI结构。在凹槽内设置氧化物填充物并被回蚀。 ONO（氧化物 - 氧化物 - 氧化物）层保形地覆盖氧化物填充物和第一多晶硅层。第二多晶硅层覆盖ONO层。凹陷内的氧化物填充提供了第二多晶硅层与STI区域的拐角之间的最小间隔，从而避免了产生弱点并降低了栅极击穿，栅极泄漏和提高器件可靠性的风险。

73. 发明授权

US06963104B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US06963104B2
公开(公告)日：2005-11-08
申请号：US10459576
申请日：2003-06-12
申请人： Yider Wu , Bin Yu
发明人： Yider Wu , Bin Yu
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/1203 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A non-volatile memory device includes a substrate, an insulating layer, a fin, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The dielectric layers are formed over the fin and the control gate is formed over the dielectric layers. The dielectric layers may include oxide-nitride-oxide layers that function as a charge storage structure for the memory device.
摘要翻译：非易失性存储器件包括衬底，绝缘层，鳍片，多个电介质层和控制栅极。绝缘层形成在基板上，并且鳍形成在绝缘层上。电介质层形成在鳍片之上，并且控制栅极形成在电介质层上。电介质层可以包括用作存储器件的电荷存储结构的氧化物 - 氮化物 - 氧化物层。

74. 发明授权

US06958512B1 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US06958512B1
公开(公告)日：2005-10-25
申请号：US10770010
申请日：2004-02-03
申请人： Yider Wu , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Yider Wu , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/788
CPC分类号： H01L29/42324 , H01L29/66795 , H01L29/785 , H01L29/7881
摘要： A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.
摘要翻译：非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。导电结构可以用作非易失性存储器件的浮栅电极。

75. 发明授权

US06933558B2 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US06933558B2
公开(公告)日：2005-08-23
申请号：US10726508
申请日：2003-12-04
申请人： Wiley Eugene Hill , Haihong Wang , Yider Wu , Bin Yu
发明人： Wiley Eugene Hill , Haihong Wang , Yider Wu , Bin Yu
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/785
摘要： A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.
摘要翻译：存储器件包括导电结构，多个电介质层和控制栅极。电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。电介质层可以包括氧化物 - 氮化物 - 氧化物层。

76. 发明授权

US06797565B1 Methods for fabricating and planarizing dual poly scalable SONOS flash memory 有权
标题翻译：双重可扩展SONOS闪存的制造和平面化方法
公开(公告)号：US06797565B1
公开(公告)日：2004-09-28
申请号：US10244369
申请日：2002-09-16
申请人： Jean Yee-Mei Yang , Yider Wu , Zhizheng Liu
发明人： Jean Yee-Mei Yang , Yider Wu , Zhizheng Liu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.
摘要翻译：公开了用于制造双位SONOS闪速存储器单元的方法，包括在ONO层上形成多晶硅栅极结构，以及使用栅极结构作为注入掩模来掺杂衬底的源极/漏极区域。还公开了在栅极结构之上和栅极结构之间形成电介质材料的方法，并且使用STI CMP工艺对晶片进行平面化以去除多晶硅栅极结构上的电介质材料。

77. 发明授权

US06607925B1 Hard mask removal process including isolation dielectric refill 有权
标题翻译：硬掩模去除工艺包括隔离介质再填充
公开(公告)号：US06607925B1
公开(公告)日：2003-08-19
申请号：US10165837
申请日：2002-06-06
申请人： Unsoon Kim , Dawn M. Hopper , Yider Wu , Krishnashree Achuthan
发明人： Unsoon Kim , Dawn M. Hopper , Yider Wu , Krishnashree Achuthan
IPC分类号： H01L2100
CPC分类号： H01L21/76224 , H01L21/0337 , H01L21/31116 , H01L21/32139
摘要： A method for repairing an isolation dielectric damaged during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material, the first material having openings therein exposing isolation regions comprising a first isolation dielectric layer. The method includes etching the hard mask material from the first material, wherein the etch creates gouges in the first isolation dielectric layer, and depositing a second layer of isolation dielectric over the first material, wherein the second isolation dielectric layer fills the gouges in the first isolation dielectric layer. The method further includes polishing on the second layer of isolation dielectric to remove the second layer of isolation dielectric from the first material.
摘要翻译：公开了一种用于修复在半导体制造工艺期间损坏的隔离电介质的方法，其中使用硬掩模材料来图案化第一材料，其中在其中具有开口的第一材料暴露出包括第一隔离介电层的隔离区域。该方法包括从第一材料蚀刻硬掩模材料，其中蚀刻在第一隔离电介质层中产生沟槽，以及在第一材料上沉积第二隔离电介质层，其中第二隔离电介质层填充第一隔离电介质层中的沟槽隔离介电层。该方法还包括在第二层隔离电介质上抛光以从第一材料去除第二隔离电介质层。

78. 发明授权

US06555436B2 Simultaneous formation of charge storage and bitline to wordline isolation 失效
公开(公告)号：US06555436B2
公开(公告)日：2003-04-29
申请号：US10223195
申请日：2002-08-19
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

79. 发明授权

US06512701B1 Erase method for dual bit virtual ground flash 有权
标题翻译：双位虚拟接地闪存的擦除方法
公开(公告)号：US06512701B1
公开(公告)日：2003-01-28
申请号：US09886861
申请日：2001-06-21
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Yider Wu
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Yider Wu
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/0475 , G11C16/0491
摘要： A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.
摘要翻译：提供了用于验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元的系统和方法。每个双位具有与第一或正常位相关联的第一或正常位和第二或补充位。系统和方法包括验证和擦除单元的正常位和互补位。擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。该组擦除脉冲由单元或晶体管结中的位的两侧的双侧擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲。

80. 发明授权

US06436768B1 Source drain implant during ONO formation for improved isolation of SONOS devices 有权
标题翻译：在ONO形成期间的源极漏极注入，以改善SONOS器件的隔离
公开(公告)号：US06436768B1
公开(公告)日：2002-08-20
申请号：US09893279
申请日：2001-06-27
申请人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
发明人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
IPC分类号： H01L21336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L27/11568 , H01L29/66833
摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
摘要翻译：本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或在电荷俘获电介质的第三层上形成附加材料。

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