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1. 发明授权

US06468865B1 Method of simultaneous formation of bitline isolation and periphery oxide 有权
标题翻译：同时形成位线隔离和周边氧化物的方法
公开(公告)号：US06468865B1
公开(公告)日：2002-10-22
申请号：US09723653
申请日：2000-11-28
申请人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.
摘要翻译：本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

2. 发明授权

US06555436B2 Simultaneous formation of charge storage and bitline to wordline isolation 失效
公开(公告)号：US06555436B2
公开(公告)日：2003-04-29
申请号：US10223195
申请日：2002-08-19
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

3. 发明授权

US06465306B1 Simultaneous formation of charge storage and bitline to wordline isolation 有权
标题翻译：同时形成电荷存储和位线到字线隔离
公开(公告)号：US06465306B1
公开(公告)日：2002-10-15
申请号：US09723635
申请日：2000-11-28
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
摘要翻译：本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 并且在芯区域和周边区域中形成栅极。

4. 发明授权

US06541816B2 Planar structure for non-volatile memory devices 失效
公开(公告)号：US06541816B2
公开(公告)日：2003-04-01
申请号：US09893026
申请日：2001-06-27
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi S. Sunkavalli , Janet S. Wang , Narbeh Derhacobian
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi S. Sunkavalli , Janet S. Wang , Narbeh Derhacobian
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

5. 发明授权

US06706595B2 Hard mask process for memory device without bitline shorts 有权
标题翻译：内存设备的硬掩模处理，无位线短路
公开(公告)号：US06706595B2
公开(公告)日：2004-03-16
申请号：US10100485
申请日：2002-03-14
申请人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Yider Wu , Emmanuil Lingunis , Tazrien Kamal
发明人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Yider Wu , Emmanuil Lingunis , Tazrien Kamal
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。硬掩模是配制用于去除而不损坏电荷捕获介电层的材料。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。生长自杀剂不会使第一和第二位线短路。

6. 发明授权

US06720133B1 Memory manufacturing process using disposable ARC for wordline formation 失效
标题翻译：使用一次性ARC进行字线形成的存储器制造过程
公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译：集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。防反射涂层是可去除的，而不会损坏电荷捕获材料。在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

7. 发明授权

US08673716B2 Memory manufacturing process with bitline isolation 有权
标题翻译：内存制造过程采用位线隔离
公开(公告)号：US08673716B2
公开(公告)日：2014-03-18
申请号：US10118732
申请日：2002-04-08
申请人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
发明人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
摘要翻译：集成电路的制造方法具有具有芯区域和周边区域的半导体基板。在芯区域中沉积电荷捕获电介质层，并且在周边区域中沉积栅极电介质层。位线在芯区域中的半导体衬底中而不是在周边区域中形成。在芯区域而不是周边区域中形成并注入掺杂剂的字线栅层。形成了一条字和门。源极/漏极结在栅极周围的半导体衬底中注入掺杂剂，栅极注入栅极掺杂注入在外围区域而不在核心区域。

8. 发明授权

US07115469B1 Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process 有权
标题翻译：使用现场蒸汽发生（ISSG）工艺的半导体器件的综合ONO处理
公开(公告)号：US07115469B1
公开(公告)日：2006-10-03
申请号：US10754948
申请日：2004-01-08
申请人： Arvind Halliyal , Mark T. Ramsbey , Hidehiko Shiraiwa , Jean Y. Yang
发明人： Arvind Halliyal , Mark T. Ramsbey , Hidehiko Shiraiwa , Jean Y. Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/3144 , H01L21/3145
摘要： A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by providing a semiconductor substrate having a silicon surface; forming a first oxide layer on the silicon surface; depositing a silicon nitride layer on the first oxide layer; and forming a top oxide layer on the silicon nitride layer, wherein the top oxide layer is formed by an in-situ steam generation oxidation of a surface of the silicon nitride layer. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate FLASH memory device including an ONO structure.
摘要翻译：一种制造包括ONO结构作为闪速存储器件的组件的半导体器件的工艺，包括通过提供具有硅表面的半导体衬底来形成ONO结构; 在硅表面上形成第一氧化物层; 在第一氧化物层上沉积氮化硅层; 以及在所述氮化硅层上形成顶部氧化物层，其中所述顶部氧化物层通过所述氮化硅层的表面的原位蒸汽发生氧化而形成。半导体器件可以是例如SONOS两位EEPROM器件或包括ONO结构的浮动栅极FLASH存储器件。

9. 发明授权

US06884681B1 Method of manufacturing a semiconductor memory with deuterated materials 有权
标题翻译：用氘代材料制造半导体存储器的方法
公开(公告)号：US06884681B1
公开(公告)日：2005-04-26
申请号：US10672093
申请日：2003-09-26
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

10. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

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