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1. 发明申请

US20070026675A1 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US20070026675A1
公开(公告)日：2007-02-01
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

2. 发明授权

US06509232B1 Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device 有权
标题翻译：闪存器件的核心和周边区域内的STI（浅沟槽隔离）结构的形成
公开(公告)号：US06509232B1
公开(公告)日：2003-01-21
申请号：US09969573
申请日：2001-10-01
申请人： Unsoon Kim , Mark S. Chang , Yider Wu , Chi Chang , Angela Hui , Yu Sun
发明人： Unsoon Kim , Mark S. Chang , Yider Wu , Chi Chang , Angela Hui , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.
摘要翻译：形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的。沉积沟槽电介质材料以填充STI开口。此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

3. 发明授权

US08093646B1 Flash memory device and method of forming the same with improved gate breakdown and endurance 有权
标题翻译：闪存器件及其形成方法具有改进的栅极击穿和耐久性
公开(公告)号：US08093646B1
公开(公告)日：2012-01-10
申请号：US11432495
申请日：2006-05-12
申请人： Angela Hui , Yider Wu
发明人： Angela Hui , Yider Wu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L29/7881
摘要： The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.
摘要翻译：本发明提供了一种闪存器件及其制造方法，其具有在衬底中形成的具有半导体衬底和浅沟槽隔离（STI）结构的浮动栅极结构。在衬底和STI结构上形成第一多晶硅层。形成在第一多晶硅层内的凹槽在STI结构之上并且延伸穿过第一多晶硅层到STI结构。在凹槽内设置氧化物填充物并被回蚀。 ONO（氧化物 - 氧化物 - 氧化物）层保形地覆盖氧化物填充物和第一多晶硅层。第二多晶硅层覆盖ONO层。凹陷内的氧化物填充提供了第二多晶硅层与STI区域的拐角之间的最小间隔，从而避免了产生弱点并降低了栅极击穿，栅极泄漏和提高器件可靠性的风险。

4. 发明申请

US20070262412A1 Avoiding Field Oxide Gouging In Shallow Trench Isolation (STI) Regions 审中-公开
标题翻译：在浅沟槽隔离（STI）区域避免场氧化物气刨
公开(公告)号：US20070262412A1
公开(公告)日：2007-11-15
申请号：US11781551
申请日：2007-07-23
申请人： Angela Hui , Jusuke Ogura , Yider Wu
发明人： Angela Hui , Jusuke Ogura , Yider Wu
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.
摘要翻译：一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。可以在STI区域中蚀刻沟槽并填充绝缘材料。抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。可以将保护盖回蚀以暴露ARC层。然而，保护盖仍然覆盖并保护绝缘材料。通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

5. 发明授权

US07067388B1 Flash memory device and method of forming the same with improved gate breakdown and endurance 失效
标题翻译：闪存器件及其形成方法具有改进的栅极击穿和耐久性
公开(公告)号：US07067388B1
公开(公告)日：2006-06-27
申请号：US10819162
申请日：2004-04-07
申请人： Angela Hui , Yider Wu
发明人： Angela Hui , Yider Wu
IPC分类号： H04L29/02
CPC分类号： H01L21/28273 , H01L29/7881
摘要： The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.
摘要翻译：本发明提供了一种闪存器件及其制造方法，其具有在衬底中形成的具有半导体衬底和浅沟槽隔离（STI）结构的浮动栅极结构。在衬底和STI结构上形成第一多晶硅层。形成在第一多晶硅层内的凹槽在STI结构之上并且延伸穿过第一多晶硅层到STI结构。在凹槽内设置氧化物填充物并被回蚀。 ONO（氧化物 - 氧化物 - 氧化物）层保形地覆盖氧化物填充物和第一多晶硅层。第二多晶硅层覆盖ONO层。凹陷内的氧化物填充提供了第二多晶硅层与STI区域的拐角之间的最小间隔，从而避免了产生弱点并降低了栅极击穿，栅极泄漏和提高器件可靠性的风险。

6. 发明授权

US08319266B1 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08319266B1
公开(公告)日：2012-11-27
申请号：US11008240
申请日：2004-12-10
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

7. 发明申请

US20110278660A1 ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB 有权
标题翻译： ORO和ORPRO与位线TRENCH到禁止运输程序干扰
公开(公告)号：US20110278660A1
公开(公告)日：2011-11-17
申请号：US13190565
申请日：2011-07-26
申请人： Ning Cheng , K.T. Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
发明人： Ning Cheng , K.T. Chang , Hiro Kinoshita , Chih-Yuh Yang , Lei Xue , Chungho Lee , Minghao Shen , Angela Hui , Huaqiang Wu
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。存储单元包含电荷存储层和第一多晶硅栅极。位线开口延伸到半导体衬底中。通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

8. 发明授权

US07951675B2 SI trench between bitline HDP for BVDSS improvement 有权
标题翻译：位线HDP之间的SI沟槽改善BVDSS
公开(公告)号：US07951675B2
公开(公告)日：2011-05-31
申请号：US11957737
申请日：2007-12-17
申请人： Lei Xue , Aimin Xing , Chih-Yuh Yang , Angela Hui , Chungho Lee
发明人： Lei Xue , Aimin Xing , Chih-Yuh Yang , Angela Hui , Chungho Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , H01L27/10885
摘要： Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.
摘要翻译：提供了具有改进的BVdss特性的存储器件和制造存储器件的方法。存储器件在半导体衬底的位线上包含位线电介质; 邻近所述位线电介质的侧表面并在所述半导体衬底的上表面上的第一间隔物; 在所述第一间隔物之间的所述半导体衬底中的沟槽; 以及邻近沟槽的侧表面的第二间隔件。通过在位线之间容纳沟槽和第一和第二间隔物，存储器件可以改善位线之间的电隔离，从而防止和/或减轻位线到位线的电流泄漏并增加BVdss。

9. 发明授权

US07622389B1 Selective contact formation using masking and resist patterning techniques 有权
标题翻译：使用掩模和抗蚀剂图案化技术的选择性接触形成
公开(公告)号：US07622389B1
公开(公告)日：2009-11-24
申请号：US11411353
申请日：2006-04-25
申请人： Kyunghoon Min , Mark Chang , Ning Cheng , Brian Osborn , Kevin Song , Fei Wang , Angela Hui , Hiroyuki Kinoshita , Kuo-Tung Chang
发明人： Kyunghoon Min , Mark Chang , Ning Cheng , Brian Osborn , Kevin Song , Fei Wang , Angela Hui , Hiroyuki Kinoshita , Kuo-Tung Chang
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/11548
摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.
摘要翻译：包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。

10. 发明申请

US20080064165A1 DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US20080064165A1
公开(公告)日：2008-03-13
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

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