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71. 发明授权

US08909871B2 Data processing system and method for reducing cache pollution by write stream memory access patterns 有权
标题翻译：用于通过写入流存储器访问模式减少高速缓存污染的数据处理系统和方法
公开(公告)号：US08909871B2
公开(公告)日：2014-12-09
申请号：US11462115
申请日：2006-08-03
申请人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
发明人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译：数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。确定存储修改操作是否具有相关的旁路指示。响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。

72. 发明授权

US08482064B2 Termination for superjunction VDMOSFET 有权
标题翻译：端接VDMOSFET
公开(公告)号：US08482064B2
公开(公告)日：2013-07-09
申请号：US13493505
申请日：2012-06-11
申请人： Yangbo Yi , Haisong Li , Qin Wang , Ping Tao , Lixin Zhang
发明人： Yangbo Yi , Haisong Li , Qin Wang , Ping Tao , Lixin Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0696
摘要： A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.
摘要翻译：硅超结VDMOSFET的终端包括也用作漏极区的重掺杂N型硅衬底; 漏极金属配置在重掺杂N型硅衬底的背表面上; 在重掺杂的N型硅衬底上设置N型硅外延层; 交替布置在N型硅外延层中形成P型硅柱和N型硅柱; 连续的氧化硅层设置在终端的硅表面的一部分上; 阻止移动离子漂移的结构（间隔布置的几个不连续的氧化硅层）设置在终端的硅表面的另一部分上。阻止设置在终端区域中的移动离子的漂移的结构能够有效地防止移动离子的移动，并提高功率器件抵抗由移动离子引起的污染的能力。

73. 发明申请

US20120191946A1 FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS 有权
标题翻译：处理器之间的快速远程通信和计算
公开(公告)号：US20120191946A1
公开(公告)日：2012-07-26
申请号：US13413787
申请日：2012-03-07
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hensbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hensbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
IPC分类号： G06F15/76 , G06F9/312
CPC分类号： G06F9/544
摘要： A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
摘要翻译：在说明性实施例中提供了用于处理器之间的快速远程通信和计算的方法。核心通信单元（DCC）的直接核心被配置为与第一处理器一起操作，第一处理器是远程处理器。与DCC相关联的存储器接收一组字节，该字节集合是从第二处理器发送的。在远程处理器中执行在该组字节中指定的操作，使得调用操作而不使软件线程执行。

74. 发明授权

US08086831B2 Indexed table circuit having reduced aliasing 有权
标题翻译：索引表电路具有减少的混叠
公开(公告)号：US08086831B2
公开(公告)日：2011-12-27
申请号：US12024241
申请日：2008-02-01
申请人： Lei Chen , Lixin Zhang
发明人： Lei Chen , Lixin Zhang
IPC分类号： G06F9/35 , G06F9/355
CPC分类号： G06F9/3848
摘要： In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.
摘要翻译：在至少一个实施例中，索引表电路包括用于存储要访问的数据的多个存储体和分离索引阵列。索引表电路被组织成多个条目，每个条目对应于多个不同入口索引中的相应一个，其中每个条目包括多个存储体中的存储位置和拆分索引阵列。索引表电路还包括选择逻辑，其响应于使用位串的条目索引的多个条目中的条目的读取访问，利用从拆分索引数组读取的拆分索引来选择一个或多个位的集合使用所选择的一个或多个位的集合来选择从多个存储体之一读取的数据，并输出所选择的数据。

75. 发明申请

US20110296428A1 REGISTER ALLOCATION TO THREADS 有权
标题翻译：注册分配到线程
公开(公告)号：US20110296428A1
公开(公告)日：2011-12-01
申请号：US12789062
申请日：2010-05-27
申请人： FREEMAN LEIGH RAWSON, III , William Evan Speight , Lixin Zhang
发明人： FREEMAN LEIGH RAWSON, III , William Evan Speight , Lixin Zhang
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/30098 , G06F9/30123 , G06F9/30138 , G06F9/384 , G06F9/5016
摘要： A method, system, and computer usable program product for improved register allocation in a simultaneous multithreaded processor. A determination is made that a thread of an application in the data processing environment needs more physical registers than are available to allocate to the thread. The thread is configured to utilize a logical register that is mapped to a memory register. The thread is executed utilizing the physical registers and the memory registers.
摘要翻译：一种用于改进同时多线程处理器中的寄存器分配的方法，系统和计算机可用程序产品。确定数据处理环境中的应用程序的线程需要比可用于分配给线程的物理寄存器更多的物理寄存器。该线程被配置为利用映射到存储器寄存器的逻辑寄存器。使用物理寄存器和存储器寄存器执行线程。

76. 发明申请

US20110021346A1 POLYMERIZATION CATALYST COMPOSITION FOR POLYMERIZATION OF ISOPRENE COMPOUND 失效
标题翻译：聚异氰酸酯化合物聚合的聚合催化剂组合物
公开(公告)号：US20110021346A1
公开(公告)日：2011-01-27
申请号：US12897750
申请日：2010-10-04
申请人： Zhaomin HOU , Lixin Zhang
发明人： Zhaomin HOU , Lixin Zhang
IPC分类号： B01J31/18
CPC分类号： C08F36/08 , C08F4/545 , C08F4/52
摘要： 3,4-isoprene-based polymer having high isotacticity can be produced by polymerizing an isoprene compound using a complex represented by the general formula (A) and a catalyst activator: wherein R1 and R2 independently represent an alkyl group, a cyclohexyl group, an aryl group or an aralkyl group; R3 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group, an aralkyl group, an aliphatic, aromatic or cyclic amino group, a phosphino group, a boryl group, an alkylthio or arylthio group, or an alkoxy or aryloxy group; M represents a rare earth element selected from Sc, Y, and La to Lu with promethium (Pm) excluded; Q1 and Q2 independently represent a monoanionic ligand; L represents a neutral Lewis base.
摘要翻译：具有高全同立构规整度的3,4-异戊二烯类聚合物可以通过使用由通式（A）表示的络合物和催化剂活化剂聚合异戊二烯化合物来制备：其中R1和R2独立地表示烷基，环己基，芳基或芳烷基; R3表示烷基，烯基，炔基，芳基，芳烷基，脂族，芳族或环状氨基，膦基，硼基，烷硫基或芳硫基，或烷氧基或芳氧基组; M表示选自Sc，Y，La至Lu的稀土元素，不含ium（Pm）; Q1和Q2独立地表示单阴离子配体; L代表中性路易斯碱。

77. 发明授权

US07829642B2 Polymerization catalyst composition for polymerization of isoprene compound 失效
标题翻译：用于异戊二烯化合物聚合的聚合催化剂组合物
公开(公告)号：US07829642B2
公开(公告)日：2010-11-09
申请号：US12282148
申请日：2007-02-05
申请人： Zhaomin Hou , Lixin Zhang
发明人： Zhaomin Hou , Lixin Zhang
IPC分类号： C08F36/08 , C08F36/04 , C08F4/44
CPC分类号： C08F36/08 , C08F4/545 , C08F4/52
摘要： 3,4-isoprene-based polymer having high isotacticity can be produced by polymerizing an isoprene compound using a complex represented by the general formula (A) and a catalyst activator: wherein R1 and R2 independently represent an alkyl group, a cyclohexyl group, an aryl group or an aralkyl group; R3 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group, an aralkyl group, an aliphatic, aromatic or cyclic amino group, a phosphino group, a boryl group, an alkylthio or arylthio group, or an alkoxy or aryloxy group; M represents a rare earth element selected from Sc, Y, and La to Lu with promethium (Pm) excluded; Q1 and Q2 independently represent a monoanionic ligand; L represents a neutral Lewis base; and w represents an integer of 0 to 3.
摘要翻译：具有高全同立构规整度的3,4-异戊二烯类聚合物可以通过使用由通式（A）表示的络合物和催化剂活化剂聚合异戊二烯化合物来制备：其中R1和R2独立地表示烷基，环己基，芳基或芳烷基; R3表示烷基，烯基，炔基，芳基，芳烷基，脂族，芳族或环状氨基，膦基，硼基，烷硫基或芳硫基，或烷氧基或芳氧基组; M表示选自Sc，Y，La至Lu的稀土元素，不含ium（Pm）; Q1和Q2独立地表示单阴离子配体; L代表中性路易斯碱; w表示0〜3的整数。

78. 发明授权

US07707396B2 Data processing system, processor and method of data processing having improved branch target address cache 失效
标题翻译：数据处理系统，处理器和数据处理方法具有改进的分支目标地址缓存
公开(公告)号：US07707396B2
公开(公告)日：2010-04-27
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

79. 发明申请

US20090287908A1 PREDICATION SUPPORT IN AN OUT-OF-ORDER PROCESSOR BY SELECTIVELY EXECUTING AMBIGUOUSLY RENAMED WRITE OPERATIONS 有权
标题翻译：通过选择性地执行经过复制的写作操作，在订单处理程序中进行预测支持
公开(公告)号：US20090287908A1
公开(公告)日：2009-11-19
申请号：US12123046
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F8/441 , G06F9/3005 , G06F9/30072 , G06F9/3842 , G06F9/3885
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译：用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。

80. 发明申请

US20090198982A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE SELECTIVELY APPLYING A DELAYED HIT 有权
标题翻译：数据处理系统，具有分支目标地址高速缓存的数据处理的处理器和方法选择性地应用延迟的HIT
公开(公告)号：US20090198982A1
公开(公告)日：2009-08-06
申请号：US12024190
申请日：2008-02-01
申请人： DAVID S. LEVITAN , Lixin Zhang
发明人： DAVID S. LEVITAN , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3869
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统中取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址预测电路，其存储将第一指令取出地址与要用作第二指令取出地址的分支目标地址相关联的分支目标地址预测。分支目标地址预测电路包括延迟逻辑，响应于与第一指令获取地址匹配的第三指令获取地址的至少一个标签部分，如果没有分支目标地址预测，则使用第二指令获取地址延迟对存储器系统的访问是在上一个操作循环中进行的。

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