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1. 发明授权

US09221838B2 Inhibitors of AKT activity 有权
标题翻译： AKT活性抑制剂
公开(公告)号：US09221838B2
公开(公告)日：2015-12-29
申请号：US13517219
申请日：2010-12-23
申请人： Lixin Zhang , Graham Peter Trevitt , Hugues Miel , Frank Burkamp , Timothy Harrison , Andrew John Wilkinson , Charles-Henry Fabritius
发明人： Lixin Zhang , Graham Peter Trevitt , Hugues Miel , Frank Burkamp , Timothy Harrison , Andrew John Wilkinson , Charles-Henry Fabritius
IPC分类号： C07D498/04 , C07D498/14 , C07D405/04 , C07D471/04
CPC分类号： C07D498/04 , C07D471/04 , C07D498/14
摘要： The invention relates to a series of compounds with particular activity as inhibitors of the serine-threonine kinase AKT. Also provided are pharmaceutical compositions comprising same as well as methods for treating cancer.
摘要翻译：本发明涉及作为丝氨酸 - 苏氨酸激酶AKT抑制剂的特定活性的一系列化合物。还提供了包含其的药物组合物以及用于治疗癌症的方法。

2. 发明申请

US20140256357A1 PROVIDING POINTS OF INTEREST TO USER DEVICES IN VARIABLE ZONES 有权
标题翻译：向可变区域中的用户设备提供兴趣点
公开(公告)号：US20140256357A1
公开(公告)日：2014-09-11
申请号：US13842088
申请日：2013-03-15
申请人： Ray Xiaohang Wang , Farhan Shamsi , Yakov Okshtein , David Singleton , Douglas Alexander Gresham , Alan Newberger , Lixin Zhang
发明人： Ray Xiaohang Wang , Farhan Shamsi , Yakov Okshtein , David Singleton , Douglas Alexander Gresham , Alan Newberger , Lixin Zhang
IPC分类号： H04W4/02
CPC分类号： H04W4/027 , G01C21/00 , G01C21/3679 , H04L67/26 , H04W4/02 , H04W4/021 , H04W4/022 , H04W4/029 , H04W4/20 , H04W4/21
摘要： Receiving point of interest zones and alerts on user devices comprises communicating, by a user computing device to a remote computing device, a request for point of interest data corresponding to points of interest within a proximity of the user device; presenting the received point of interest data; identifying a particular point of interest; and outputting an alert regarding the particular point of interest. Receiving point of interest zones on user devices comprises communicating a request for point of interest data; receiving the point of interest data from the remote network device wherein a size of the point of interest zone is determined based on a density of points of interest in the proximity of the user, and wherein the shape of the point of interest zone is expanded in a direction of travel and contracted in the opposite direction; and presenting the received point of interest data.
摘要翻译：在用户设备上接收兴趣点区域和警报包括由用户计算设备向远程计算设备通知与用户设备附近的兴趣点对应的兴趣点数据的请求; 呈现接收的兴趣点数据; 识别一个特定的兴趣点; 并输出关于特定兴趣点的警报。在用户设备上接收兴趣点区域包括传送关于兴趣点数据的请求; 从所述远程网络设备接收所述兴趣点数据，其中，基于所述用户附近的兴趣点的密度来确定所述兴趣点区域的大小，并且其中所述兴趣点区域的形状在旅行方向与方向相反; 并呈现所接收的兴趣点数据。

3. 发明申请

US20140243342A1 COMPOSITIONS AND METHODS FOR PROPHYLAXIS AND THERAPY FOR MENIERES DISEASE 审中-公开
标题翻译：预防和治疗男性疾病的组合物和方法
公开(公告)号：US20140243342A1
公开(公告)日：2014-08-28
申请号：US14183148
申请日：2014-02-18
申请人： Lixin Zhang
发明人： Lixin Zhang
IPC分类号： A61K31/53 , A61K31/137
CPC分类号： A61K31/53 , A61K31/137 , A61K2300/00
摘要： Provided are articles of manufacture, compositions and methods for prophylaxis and/or therapy for disorders involving dizziness and/or vertigo. The articles of manufacture and compositions contain lamotrigine and/or bupropion and pharmaceutically acceptable salts thereof. The compositions include pharmaceutical compositions which are intended to alleviate dizziness and/or vertigo. In certain aspects the disclosure includes articles of manufacture and kits which include printed material which provides an indication that the articles or compositions are intended to be used for prophylaxis and/or therapy of Meniere's disease or a symptom thereof.
摘要翻译：提供了涉及眩晕和/或眩晕的疾病的预防和/或治疗的制品，组合物和方法。制品和组合物含有拉莫三嗪和/或安非他酮及其药学上可接受的盐。组合物包括旨在减轻眩晕和/或眩晕的药物组合物。在某些方面，本公开包括制品和试剂盒，其包括印刷材料，其提供用于预防和/或治疗梅尼埃病或其症状的制品或组合物的指示。

4. 发明授权

US08783198B2 Spar hull belly strake design and installation method 有权
标题翻译： Spar船体腹部设计和安装方法
公开(公告)号：US08783198B2
公开(公告)日：2014-07-22
申请号：US13147256
申请日：2010-01-28
申请人： Michael Y. H. Luo , Lixin Zhang , Kostas Filoktitis Lambrakos , Vera Mohr
发明人： Michael Y. H. Luo , Harvey O. Mohr , Lixin Zhang , Kostas Filoktitis Lambrakos
IPC分类号： F15D1/10
CPC分类号： B63B1/048 , B63B35/4406 , B63B39/005 , B63B2035/442
摘要： A spar hull for a floating vessel can include a hard tank having a belly portion, a fixed strake coupled to the outer surface of the tank and a folding strake coupled to the belly portion of the tank, the folding strake having one or more strake panels and one or more support frames. A method for installing folding belly strakes on a spar hull may include providing a floating spar hull having a hard tank with a belly side, rotating the spar so that the belly side is in a first workable position, coupling at least one folding strake to the belly side of the spar, and coupling the strake in a folded position for transport. The method may include positioning the spar hull offshore in a transport position, upending the spar hull, unfolding the strake, fixing the strake in the unfolded position and installing the spar hull.
摘要翻译：用于浮动船只的翼梁可以包括具有腹部的硬罐，耦合到罐的外表面的固定板条和耦合到罐的腹部的折叠板，折叠板具有一个或多个板条板和一个或多个支撑框架。用于在翼梁上安装折叠式腹板的方法可以包括：提供具有带有腹部侧面的硬罐的浮动翼梁，旋转翼梁使得腹部侧处于第一可操作位置，将至少一个折叠板连接到翼梁的腹部侧面，并将平台连接在折叠位置以便运输。该方法可以包括将桨叶船体近海定位在运输位置，从而升高翼梁船体，展开船形板，将船板固定在展开位置并安装翼梁船体。

5. 发明授权

US08612691B2 Assigning memory to on-chip coherence domains 有权
标题翻译：将内存分配给片上相干域
公开(公告)号：US08612691B2
公开(公告)日：2013-12-17
申请号：US13454814
申请日：2012-04-24
申请人： William E. Speight , Lixin Zhang
发明人： William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.
摘要翻译：将存储器分配给片上高速缓存一致性域的机制将处理单元内的高速缓存分配给相干域。该机制将大块内存分配给一致性域。该机制监视在处理单元内的核心上运行的应用程序，以识别应用程序的需求。然后，该机制可以基于在相干域中运行的应用的需要将存储器块重新分配给高速缓存一致性域。当存储器控制器接收高速缓存未命中时，存储器控制器可以查找映射存储器块到高速缓存一致性域的查找表中的地址。侦听请求被发送到连贯域内的缓存。如果在相干域内的高速缓存中找到高速缓存行，则通过直接或通过存储器控制器的高速缓存行的高速缓存将高速缓存行返回到始发高速缓存。

6. 发明申请

US20130069155A1 Termination for Superjunction VDMOSFET 有权
标题翻译：超结VDMOSFET的终止
公开(公告)号：US20130069155A1
公开(公告)日：2013-03-21
申请号：US13493505
申请日：2012-06-11
申请人： Yangbo YI , Haisong LI , Qin WANG , Ping TAO , Lixin ZHANG
发明人： Yangbo YI , Haisong LI , Qin WANG , Ping TAO , Lixin ZHANG
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0696
摘要： A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.
摘要翻译：硅超结VDMOSFET的终端包括也用作漏极区的重掺杂N型硅衬底; 漏极金属配置在重掺杂N型硅衬底的背表面上; 在重掺杂的N型硅衬底上设置N型硅外延层; 交替布置在N型硅外延层中形成P型硅柱和N型硅柱; 连续的氧化硅层设置在终端的硅表面的一部分上; 阻止移动离子漂移的结构（间隔布置的几个不连续的氧化硅层）设置在终端的硅表面的另一部分上。阻止设置在终端区域中的移动离子的漂移的结构能够有效地防止移动离子的移动，并提高功率器件抵抗由移动离子引起的污染的能力。

7. 发明授权

US08386690B2 On-chip networks for flexible three-dimensional chip integration 有权
标题翻译：片上网络为灵活的三维芯片集成
公开(公告)号：US08386690B2
公开(公告)日：2013-02-26
申请号：US12617859
申请日：2009-11-13
申请人： Jian Li , Steven P. VanderWiel , Lixin Zhang
发明人： Jian Li , Steven P. VanderWiel , Lixin Zhang
IPC分类号： G06F13/00 , H01L25/00
CPC分类号： G06F15/7842
摘要： Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.
摘要翻译：提供具有多个独立和协作的片上网络的具有三维集成电路器件的互连层的机构。关于实现互连层的装置，这种装置包括包含一个或多个第一功能单元和耦合到第一集成电路层的互连层的第一集成电路层。第一集成电路层和互连层彼此集成为单个三维集成电路。互连层包括多个独立的片上通信网络，这些独立的片上通信网络是独立可操作的并且独立地能够通电和关断，每个片上通信网络包括多个点对点通信链路，多个点对点通信链路通过多个连接点。一个或多个第一功能单元耦合到互连层的第一独立片上通信网络。

8. 发明授权

US08310936B2 Link services in a communication network 失效
标题翻译：在通信网络中链接服务
公开(公告)号：US08310936B2
公开(公告)日：2012-11-13
申请号：US12178048
申请日：2008-07-23
申请人： Jian Li , Lixin Zhang
发明人： Jian Li , Lixin Zhang
IPC分类号： H04L12/28
CPC分类号： H04L12/12 , Y02D50/30 , Y02D50/40
摘要： In a communication network, links in a transmission path between source and destination terminals are sequentially switched to an operational state in response to a command or a group of commands for transmitting data prior to completion of assembling the data. Each node in the transmission path independently monitors transmission of data. After transmitting the data, the links are selectively switched to pre-determined power saving states.
摘要翻译：在通信网络中，响应于在组装数据之前发送数据的命令或一组命令，在源终端和目的终端之间的传输路径中的链路被顺序地切换到操作状态。传输路径中的每个节点都独立地监视数据的传输。在发送数据之后，链路被选择性地切换到预定的省电状态。

9. 发明授权

US08250307B2 Sourcing differing amounts of prefetch data in response to data prefetch requests 失效
标题翻译：根据数据预取请求采购不同数量的预取数据
公开(公告)号：US08250307B2
公开(公告)日：2012-08-21
申请号：US12024165
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。预取加载请求指定所请求的数据行。响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。

10. 发明授权

US08250298B2 Mechanisms for reducing DRAM power consumption 失效
标题翻译：降低DRAM功耗的机制
公开(公告)号：US08250298B2
公开(公告)日：2012-08-21
申请号：US12789019
申请日：2010-05-27
申请人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
发明人： Elmootazbellah N. Elnozahy , Karthick Rajamani , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G11C11/406 , G11C11/4094 , G11C2211/4065 , G11C2211/4067 , Y02D10/13 , Y02D10/14
摘要： Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
摘要翻译：提供用于禁止动态随机存取存储器（DRAM）结构的存储器单元的预充电的机制。这些机制接收到用于访问DRAM结构的存储单元的命令。这些机制基于该命令进一步确定如果禁止在访问存储器单元之后对存储单元进行预充电。此外，机构响应于指示要禁止对存储器单元进行预充电的确定，发送阻止DRAM结构的逻辑以阻止访问存储器单元之后的存储器单元的预充电的命令。

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