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    • 4. 发明申请
    • System and method of managing cache hierarchies with adaptive mechanisms
    • 用自适应机制管理缓存层次的系统和方法
    • US20060277366A1
    • 2006-12-07
    • US11143328
    • 2005-06-02
    • Ramakrishnan RajamonyHazim ShafiWilliam SpeightLixin Zhang
    • Ramakrishnan RajamonyHazim ShafiWilliam SpeightLixin Zhang
    • G06F12/00
    • G06F12/0897G06F12/0817G06F12/0822
    • A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.
    • 一种使用自适应机制管理缓存层次结构的系统和方法。 本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存(源高速缓存)中选择用于逐出的数据块,检查数据结构以确定是否存在指示数据 块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器,并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。 此外,本发明的优选实施例包括响应于确定条目存在于数据结构中,从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块 内存缓存被驱逐。
    • 6. 发明申请
    • Just-In-Time Prefetching
    • 即时预取
    • US20070283101A1
    • 2007-12-06
    • US11422459
    • 2006-06-06
    • Wael R. El-EssawyRamakrishnan RajamonyHazim ShafiWilliam E. SpeightLixin Zhang
    • Wael R. El-EssawyRamakrishnan RajamonyHazim ShafiWilliam E. SpeightLixin Zhang
    • G06F12/00
    • G06F12/0862
    • A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
    • 一种用于在包括处理器,高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置,以及至少一个存储器存储装置。 该装置包括预取引擎,具有用于发出数据预取请求的装置,用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序,用于动态地调整数据预取请求的预取引擎的发布之间的预取距离,并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求(加载请求) 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。
    • 7. 发明授权
    • System and method of managing cache hierarchies with adaptive mechanisms
    • 用自适应机制管理缓存层次的系统和方法
    • US07281092B2
    • 2007-10-09
    • US11143328
    • 2005-06-02
    • Ramakrishnan RajamonyHazim ShafiWilliam E. SpeightLixin Zhang
    • Ramakrishnan RajamonyHazim ShafiWilliam E. SpeightLixin Zhang
    • G06F12/00
    • G06F12/0897G06F12/0817G06F12/0822
    • A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.
    • 一种使用自适应机制管理缓存层次结构的系统和方法。 本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存(源高速缓存)中选择用于逐出的数据块,检查数据结构以确定是否存在指示数据 块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器,并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。 此外,本发明的优选实施例包括响应于确定条目存在于数据结构中,从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块 内存缓存被驱逐。
    • 10. 发明授权
    • Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system
    • 动态调整预取距离,以便在处理系统中实现即时预取
    • US07487297B2
    • 2009-02-03
    • US11422459
    • 2006-06-06
    • Wael R. El-EssawyRamakrishnan RajamonyHazim ShafiWilliam E. SpeightLixin Zhang
    • Wael R. El-EssawyRamakrishnan RajamonyHazim ShafiWilliam E. SpeightLixin Zhang
    • G06F13/00
    • G06F12/0862
    • A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
    • 一种用于在包括处理器,高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置,以及至少一个存储器存储装置。 该装置包括预取引擎,具有用于发出数据预取请求的装置,用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序,用于动态地调整数据预取请求的预取引擎的发布之间的预取距离,并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求(加载请求) 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。