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1. 发明申请

US20090183127A1 Method and Apparatus for Evaluating Integrated Circuit Design Performance Using Enhanced Basic Block Vectors that Include Data Dependent Information 有权
标题翻译：使用包含数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置
公开(公告)号：US20090183127A1
公开(公告)日：2009-07-16
申请号：US11972747
申请日：2008-01-11
申请人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell , Thomas W. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。基准软件从应用软件的指令轨迹生成基本块向量BBV。基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。

2. 发明申请

US20080256347A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PATH-CORRELATED INDIRECT ADDRESS PREDICTIONS 有权
标题翻译：用于路径相关的间接地址预测的方法，系统和计算机程序产品
公开(公告)号：US20080256347A1
公开(公告)日：2008-10-16
申请号：US11734519
申请日：2007-04-12
申请人： Richard J. Eickemeyer , Michael K. Gschwind , Ravi Nair , Robert A. Philhower
发明人： Richard J. Eickemeyer , Michael K. Gschwind , Ravi Nair , Robert A. Philhower
IPC分类号： G06F9/30
CPC分类号： G06F9/3848
摘要： A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted into a path history register by shifting bits in the path history register and/or applying a hash operation, information corresponding to prior history is removed from the path history register, using a shift out operation and/or a hash operation. The path, history register is used to maintain a recent target, table and generate register-indirect branch target address predictions based on path history correlation between register-indirect branches captured by the path history register.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于维护寄存器间接分支的路径历史寄存器。使用命中选择和/或散列函数操作，基于一组目标地址位产生一组位，并且通过将路径历史寄存器中的位移位和/或将该生成的位组插入到路径历史寄存器中使用散列操作，使用移出操作和/或散列操作从路径历史寄存器中移除与先前历史相对应的信息。路径历史寄存器用于维护最近的目标，表格，并根据由路径历史寄存器捕获的寄存器间接分支之间的路径历史相关性生成寄存器间接分支目标地址预测。

3. 发明授权

US5355460A In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution 失效
标题翻译：内存预处理器，用于复合并行计算机系统执行指令序列
公开(公告)号：US5355460A
公开(公告)日：1994-10-11
申请号：US98240
申请日：1993-07-29
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis , Bartholomew Blaner
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis , Bartholomew Blaner
IPC分类号： G06F15/00 , G06F9/00 , G06F9/38 , G06F13/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译：一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有用于存储包括计算机指令的信息块的主存储单元，包括用于分析指令的指令复合单元，并向每个指令添加指示是否指示的指示字段该指令可以与另一个相邻指令并行处理。标记的指令存储在主存储器中。计算机系统还包括彼此并行操作的多个功能指令处理单元。提供给功能单元的指令通过高速缓存存储单元从存储器获得。在指令发布时，根据其操作代码字段的编码，检查指令的标签字段并将用于并行处理的标记字段发送到不同的功能单元。

4. 发明授权

US07707396B2 Data processing system, processor and method of data processing having improved branch target address cache 失效
标题翻译：数据处理系统，处理器和数据处理方法具有改进的分支目标地址缓存
公开(公告)号：US07707396B2
公开(公告)日：2010-04-27
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

5. 发明申请

US20080307203A1 Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces 失效
标题翻译：缩放指令间隔以识别代表性指令跟踪的收集点
公开(公告)号：US20080307203A1
公开(公告)日：2008-12-11
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译：提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。针对一组阶段中的每个阶段计算相位指令预算。相位指令预算基于与每个阶段相关联的权重和全局指令预算。为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。确定区间指标集内的指令是否符合全球指令预算。响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

6. 发明申请

US20080229068A1 ADAPTIVE FETCH GATING IN MULTITHREADED PROCESSORS, FETCH CONTROL AND METHOD OF CONTROLLING FETCHES 审中-公开
标题翻译：多用途处理器中的自适应FETCH加权，FETCH控制和控制FETCH的方法
公开(公告)号：US20080229068A1
公开(公告)日：2008-09-18
申请号：US12106360
申请日：2008-04-21
申请人： PRADIP BOSE , ALPER BUYUKTOSUNOGLU , RICHARD J. EICKEMEYER , LEE E. EISEN , PHILIP G. EMMA , JOHN B. GRISWELL , ZHIGANG HU , HUNG Q. LE , DOUGLAS R. LOGAN , BALARAM SINHAROY
发明人： PRADIP BOSE , ALPER BUYUKTOSUNOGLU , RICHARD J. EICKEMEYER , LEE E. EISEN , PHILIP G. EMMA , JOHN B. GRISWELL , ZHIGANG HU , HUNG Q. LE , DOUGLAS R. LOGAN , BALARAM SINHAROY
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signals are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）信号，用于指示流水线执行线程状态的下游流水线条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

7. 发明授权

US6088788A Background completion of instruction and associated fetch request in a multithread processor 失效
标题翻译：在多线程处理器中完成指令和相关的提取请求
公开(公告)号：US6088788A
公开(公告)日：2000-07-11
申请号：US773572
申请日：1996-12-27
申请人： John M. Borkenhagen , Richard J. Eickemeyer , Sheldon B. Levenstein , Andrew H. Wottreng , Duane A. Averill , James I. Brookhouser
发明人： John M. Borkenhagen , Richard J. Eickemeyer , Sheldon B. Levenstein , Andrew H. Wottreng , Duane A. Averill , James I. Brookhouser
IPC分类号： G06F9/38 , G06F9/40 , G06F15/76
CPC分类号： G06F9/3851 , G06F9/3824
摘要： The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled. After the requested data returns from higher level memory, the storage control unit will dispatch the instruction from the first thread having received the cache miss to an unused slot in the storage pipeline. Consequently, this instruction from the first thread will be processed along with the instructions from the second thread.
摘要翻译：数据处理系统包括形成多个处理流水线的多个执行单元。多个处理管线处理指令并且包括存储管线。数据处理系统还包括指令单元和存储控制单元。指令单元向多个执行单元输出指令，并且控制多个执行单元执行多个线程。如果存储管线中的第一线程的指令经历高速缓存未命中并且指令单元决定切换线程，则指令单元开始处理第二线程。指令单元还向存储控制单元发出数据请求以获得丢失的数据。在处理第二个线程期间，未使用的插槽将出现在存储管道中，因为不可能总是调度指令以完全保持管道的填充。在所请求的数据从较高级存储器返回之后，存储控制单元将从接收到高速缓存未命中的第一线程的指令发送到存储流水线中的未使用的时隙。因此，来自第一个线程的指令将与第二个线程的指令一起处理。

8. 发明授权

US5500942A Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions 失效
标题翻译：基于假设指令分析指示标量指令的并行执行复合性的方法
公开(公告)号：US5500942A
公开(公告)日：1996-03-19
申请号：US457765
申请日：1995-06-01
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3808 , G06F9/30149 , G06F9/30152 , G06F9/3816 , G06F9/3842 , G06F9/3853
摘要： This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions which qualify need to have appropriate tags to indicate they are candidates for compounding. In System 370 where instructions are either 2, 4 or 6 bytes in length, the field positions for the OP Code are presumed based on an estimated instruction length code. The value of each tag based on a presumed OP Code is recorded, and the instruction length code in the presumed OP Code is used to locate a complete sequence of possible instructions. Once an actual instruction boundary is found, the corresponding correct tag values are used to identify the commencement of a compound instruction, and other incorrectly generated tags are ignored.
摘要翻译：这是一种从指令流中复合两个或多个指令而不知道每个单独指令的起始点或长度的方法。所有指令在预定字段位置包括一个OP代码，用于标识指令及其长度。那些符合条件的指令需要有适当的标签来表明它们是复合的候选者。在系统370中，其中指令长度为2,4或6字节，则基于估计的指令长度代码来推定OP代码的字段位置。记录基于假设的OP代码的每个标签的值，并且使用推定的OP代码中的指令长度代码来定位可能的指令的完整序列。一旦发现了实际的指令边界，则使用相应的正确标签值来识别复合指令的开始，并忽略其他错误生成的标签。

9. 发明授权

US5442767A Address prediction to avoid address generation interlocks in computer systems 失效
标题翻译：地址预测，以避免计算机系统中的地址生成互锁
公开(公告)号：US5442767A
公开(公告)日：1995-08-15
申请号：US965466
申请日：1992-10-23
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis
IPC分类号： G06F9/32 , G06F9/345 , G06F9/38 , G06F12/00
CPC分类号： G06F9/325 , G06F9/345 , G06F9/383 , G06F9/3832
摘要： A computer system predicts an address required to execute a current iteration of a program instruction based on addresses required to execute previous iterations of the same program instruction. The system stores an address required to execute the previous iteration of the program instruction, and determines differences between addresses required to execute successive iterations of the program instruction prior to the current iteration. The system also determines and stores a current value of a delta, and predicts the address required to execute the current iteration of the program instruction based on the address required to execute the previous iteration of the program instruction plus the current value of the delta. The system sets the delta at one time equal to a difference between two addresses required to execute two successive iterations of the program instruction and updates delta when two actual differences between three addresses required to execute three successive iterations of the program instruction are equal to each other and different than delta. Thus, the system predicts constantly spaced addresses unless two successive addresses have a different spacing than the previous address. This is particularly advantageous when the program instruction adds data stored as elements of rows of one or more matrices. While the prediction will be incorrect for the first element in each row (and the first two elements in the first row) of each matrix, the prediction will be correct for all other elements in the rows, even if the inter-element spacings in rows of the different matrices are different than each other. For each of some predictions for successive iterations of the program instruction, the system negates the current value of the delta, whereby the predictions alternate between two addresses for multiple iterations of the program instruction.
摘要翻译：计算机系统基于执行相同程序指令的先前迭代所需的地址来预测执行程序指令的当前迭代所需的地址。系统存储执行程序指令的先前迭代所需的地址，并且确定在当前迭代之前执行程序指令的连续迭代所需的地址之间的差异。该系统还确定并存储增量的当前值，并且基于执行程序指令的先前迭代加上增量的当前值所需的地址来预测执行程序指令的当前迭代所需的地址。该系统一次将增量设置为等于执行程序指令的两个连续迭代所需的两个地址之间的差异，并且当执行程序指令的三个连续迭代所需的三个地址之间的两个实际差异彼此相等时更新增量并不同于三角洲。因此，系统预测不间断的地址，除非两个连续的地址具有与先前地址不同的间隔。当程序指令添加存储为一个或多个矩阵的行的元素的数据时，这是特别有利的。虽然对于每个矩阵的每行（和第一行中的前两个元素）的第一个元素的预测将是不正确的，但是对于行中的所有其他元素，预测将是正确的，即使行中的元素间隔的不同矩阵彼此不同。对于程序指令的连续迭代的一些预测中的每一个，系统否定增量的当前值，由此预测在程序指令的多次迭代的两个地址之间交替。

10. 发明授权

US07392366B2 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US07392366B2
公开(公告)日：2008-06-24
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

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