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1. 发明申请

US20090198982A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE SELECTIVELY APPLYING A DELAYED HIT 有权
标题翻译：数据处理系统，具有分支目标地址高速缓存的数据处理的处理器和方法选择性地应用延迟的HIT
公开(公告)号：US20090198982A1
公开(公告)日：2009-08-06
申请号：US12024190
申请日：2008-02-01
申请人： DAVID S. LEVITAN , Lixin Zhang
发明人： DAVID S. LEVITAN , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3869
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统中取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址预测电路，其存储将第一指令取出地址与要用作第二指令取出地址的分支目标地址相关联的分支目标地址预测。分支目标地址预测电路包括延迟逻辑，响应于与第一指令获取地址匹配的第三指令获取地址的至少一个标签部分，如果没有分支目标地址预测，则使用第二指令获取地址延迟对存储器系统的访问是在上一个操作循环中进行的。

2. 发明授权

US07844807B2 Branch target address cache storing direct predictions 失效
标题翻译：分支目标地址缓存存储直接预测
公开(公告)号：US07844807B2
公开(公告)日：2010-11-30
申请号：US12024197
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/35 , G06F9/355 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元和指令排序逻辑，其提取由执行单元执行的指令。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址高速缓存（BTAC），其具有至少一个直接条目，为直接分支目标地址预测提供存储，该直接分支目标地址预测将第一指令获取地址与分支目标地址相关联，以将分配目标地址紧随在第二指令获取地址之后第一指令获取地址和至少一个间接条目提供用于间接分支目标地址预测的存储，用于将第三指令获取地址与分支目标地址相关联，以将分配目标地址用作第三指令提取地址和中间地址之后的第四指令获取地址第五指令提取地址。

3. 发明授权

US07962722B2 Branch target address cache with hashed indices 有权
标题翻译：具有散列索引的分支目标地址缓存
公开(公告)号：US07962722B2
公开(公告)日：2011-06-14
申请号：US12024219
申请日：2008-02-01
申请人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
发明人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到至少一个执行单元的指令和指令排序逻辑，其从存储器系统取出用于由至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址高速缓存（BTAC），其包括用于存储分支目标地址预测的多个条目。 BTAC包括索引逻辑，其基于指令地址的至少一组较高位和指令地址的较低位的集合来选择使用BTAC索引的访问条目。

4. 发明申请

US20090049286A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING IMPROVED BRANCH TARGET ADDRESS CACHE 失效
标题翻译：数据处理系统，具有改进的分支目标地址高速缓存的数据处理的处理器和方法
公开(公告)号：US20090049286A1
公开(公告)日：2009-02-19
申请号：US11837893
申请日：2007-08-13
申请人： David S. Levitan , William E. Speight , Lixin Zhang
发明人： David S. Levitan , William E. Speight , Lixin Zhang
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.
摘要翻译：处理器包括执行单元和从存储器系统执行指令的指令排序逻辑。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括一级分支目标地址高速缓存（BTAC）和二级BTAC，每级具有相应的多个条目，每个条目将至少一个标签与预测的分支目标地址相关联。分支逻辑与第一指令获取地址的标签部分并行地访问一级和二级BTAC以从第一级BTAC获得第一预测分支目标地址，以在第一处理器时钟周期中用作第二指令获取地址以及来自第二级BTAC的第二预测分支目标地址，以在随后的第二处理器时钟周期中用作第三指令提取地址。

5. 发明授权

US07877586B2 Branch target address cache selectively applying a delayed hit 有权
标题翻译：分支目标地址缓存有选择地应用延迟命中
公开(公告)号：US07877586B2
公开(公告)日：2011-01-25
申请号：US12024190
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/32 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3869
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址预测电路，其存储将第一指令取出地址与要用作第二指令取出地址的分支目标地址相关联的分支目标地址预测。分支目标地址预测电路包括延迟逻辑，响应于与第一指令获取地址匹配的第三指令获取地址的至少一个标签部分，如果没有分支目标地址预测，则使用第二指令获取地址延迟对存储器系统的访问是在上一个操作循环中进行的。

6. 发明授权

US07865705B2 Branch target address cache including address type tag bit 有权
标题翻译：分支目标地址缓存包括地址类型标签位
公开(公告)号：US07865705B2
公开(公告)日：2011-01-04
申请号：US12024203
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/35 , G06F9/355
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/30174 , G06F9/3802 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3889
摘要： In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括执行单元和指令排序逻辑，其从存储器系统中取出指令以供执行单元执行。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址预测电路，同时保持提供用于第一分支目标地址预测的存储的第一条目，其中第一分支目标地址预测将第一指令获取地址与要用作指令获取地址的第一转移目标地址相关联，以及第二条目提供存储用于将第一指令提取地址与不同的第二分支目标地址相关联的第二分支目标地址预测。第一条目指示第一指令获取地址的第一指令地址类型，第二条目指示第一指令提取地址的第二指令地址类型。

7. 发明申请

US20090198985A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE WITH HASHED INDICES 有权
标题翻译：数据处理系统，具有分散目标地址缓存的数据处理器和数据处理方法
公开(公告)号：US20090198985A1
公开(公告)日：2009-08-06
申请号：US12024219
申请日：2008-02-01
申请人： SHELDON B. LEVENSTEIN , David S. Levitan , Lixin Zhang
发明人： SHELDON B. LEVENSTEIN , David S. Levitan , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址高速缓存（BTAC），其包括用于存储分支目标地址预测的多个条目。 BTAC包括索引逻辑，其基于指令地址的至少一组较高位和指令地址的较低位的集合来选择使用BTAC索引的访问条目。

8. 发明授权

US07783870B2 Branch target address cache 失效
标题翻译：分支目标地址缓存
公开(公告)号：US07783870B2
公开(公告)日：2010-08-24
申请号：US11837893
申请日：2007-08-13
申请人： David S. Levitan , William E. Speight , Lixin Zhang
发明人： David S. Levitan , William E. Speight , Lixin Zhang
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.
摘要翻译：处理器包括执行单元和从存储器系统执行指令的指令排序逻辑。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括一级分支目标地址高速缓存（BTAC）和二级BTAC，每级具有相应的多个条目，每个条目将至少一个标签与预测的分支目标地址相关联。分支逻辑与第一指令获取地址的标签部分并行地访问一级和二级BTAC以从第一级BTAC获得第一预测分支目标地址，以在第一处理器时钟周期中用作第二指令获取地址以及来自第二级BTAC的第二预测分支目标地址，以在随后的第二处理器时钟周期中用作第三指令提取地址。

9. 发明授权

US09197550B2 Method and device for determining forwarding rule for data packet 有权
标题翻译：确定数据包转发规则的方法和装置
公开(公告)号：US09197550B2
公开(公告)日：2015-11-24
申请号：US13513959
申请日：2009-12-17
申请人： Lixin Zhang , Duan Chen , Lijun Chen
发明人： Lixin Zhang , Duan Chen , Lijun Chen
IPC分类号： H04L12/28 , H04L12/723 , H04L12/46 , H04L12/721
CPC分类号： H04L45/50 , H04L12/4625 , H04L12/4641 , H04L45/66 , H04L45/68
摘要： A method and corresponding device for determining forwarding rule for data packet in Virtual Private LAN Service with Provider Backbone Bridge (PBB-VPLS) network are disclosed. In the method, a value in a backbone service instance identifier (I-SID) field of the received data packet is firstly examined, then a virtual split horizon group corresponding to the data packets is determined based on the I-SID value, wherein the virtual split horizon group defines a forwarding rule for the data packets between different pseudo wire ports of the PBB-VPLS network. With the dynamic split horizon group, the method dynamically adapts to different forwarding rules for multiple I-VPLS instances with different tree topologies, and is capable of supporting multiple I-VPLS instances with different root sites and tree topologies in one B-VPLS instance, thereby ensuring the stability of the backbone network and reducing the network operation cost.
摘要翻译：公开了一种用于确定具有提供商骨干桥（PBB-VPLS）网络的虚拟专用LAN服务中的数据分组的转发规则的方法和相应设备。在该方法中，首先检查接收到的数据分组的骨干服务实例标识符（I-SID）字段中的值，然后基于I-SID值确定与数据分组对应的虚拟水平分割组，其中，虚拟水平分割组为PBB-VPLS网络的不同伪线端口之间的数据包定义了转发规则。利用动态水平分割组，该方法动态适应不同树拓扑的多个I-VPLS实例的不同转发规则，并且能够在一个B-VPLS实例中支持具有不同根站点和树形拓扑的多个I-VPLS实例，从而确保骨干网的稳定性，降低网络运营成本。

10. 发明授权

US08966219B2 Address translation through an intermediate address space 有权
标题翻译：通过中间地址空间进行地址转换
公开(公告)号：US08966219B2
公开(公告)日：2015-02-24
申请号：US11928125
申请日：2007-10-30
申请人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1072
摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.
摘要翻译：在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。使用中间地址访问高速缓冲存储器。响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。使用实际地址访问系统内存。

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