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1. 发明授权

US08856453B2 Persistent prefetch data stream settings 有权
标题翻译：持久性预取数据流设置
公开(公告)号：US08856453B2
公开(公告)日：2014-10-07
申请号：US13410260
申请日：2012-03-01
申请人： Jason N. Dale , Miles R. Dooley , Richard J. Eickemeyer , Bradly G. Frey , Yaoqing Gao , Francis P. O'Connell , Jeffrey A. Stuecheli
发明人： Jason N. Dale , Miles R. Dooley , Richard J. Eickemeyer , Bradly G. Frey , Yaoqing Gao , Francis P. O'Connell , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/6028
摘要： A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.
摘要翻译：预取单元包括一个过渡寄存器和一个长度寄存器。 Transient寄存器容纳数据流预取的瞬态指示。长度寄存器托管用于数据流预取的流长度的指示。预取单元监视临时寄存器和长度寄存器。当Transient寄存器指示瞬态时，预取单元产生具有直到流长度限制的瞬态特性的数据流的预取请求，并且长度寄存器指示数据流预取的流长度限制。与预取单元耦合的高速缓存控制器实现高速缓存替换策略和高速缓存一致性协议。高速缓存控制器将响应于预取请求的从存储器提供的数据写入高速缓存中，并显示瞬时信号。高速缓存控制器使高速缓存行受到与缓存替换策略无关的暂态指示。

2. 发明申请

US20120084511A1 INEFFECTIVE PREFETCH DETERMINATION AND LATENCY OPTIMIZATION 有权
标题翻译：无意义的预先确定和延期优化
公开(公告)号：US20120084511A1
公开(公告)日：2012-04-05
申请号：US12897008
申请日：2010-10-04
申请人： Miles R. Dooley , Venkat R. Indukuru , Alex E. Mericas , Francis P. O'Connell
发明人： Miles R. Dooley , Venkat R. Indukuru , Alex E. Mericas , Francis P. O'Connell
IPC分类号： G06F12/08 , G06F9/38 , G06F9/30
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/383 , G06F12/0897 , G06F2212/6024
摘要： A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyses the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the infectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.
摘要翻译：信息处理系统（IHS）的处理器在指令处理期间响应于需求负载启动L3高速缓存预取操作。处理器随机选择L3高速缓存预取作为目标预取指令进行跟踪。处理器发起L1高速缓存目标预取操作，并将所得到的目标预取指令存储在L1高速缓存中。如果需求负载到达，则处理器分析目标预取指令的有效性并确定预取数据的来源。如果请求没有到达，则处理器测试以确定特定预取指令是否在高速缓存中超时并且识别预取操作的感染性。处理器随机抽取多个预取操作，并生成预取有效性和其他有用的预取信息的历史记录。处理器存储预取有效性信息以便能够减少或去除无效的预取操作。

3. 发明申请

US20080046736A1 Data Processing System and Method for Reducing Cache Pollution by Write Stream Memory Access Patterns 有权
标题翻译：数据处理系统和通过写入流存储器访问模式减少高速缓存污染的方法
公开(公告)号：US20080046736A1
公开(公告)日：2008-02-21
申请号：US11462115
申请日：2006-08-03
申请人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
发明人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
IPC分类号： H04L9/00
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译：数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。确定存储修改操作是否具有相关的旁路指示。响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。

4. 发明授权

US08909871B2 Data processing system and method for reducing cache pollution by write stream memory access patterns 有权
标题翻译：用于通过写入流存储器访问模式减少高速缓存污染的数据处理系统和方法
公开(公告)号：US08909871B2
公开(公告)日：2014-12-09
申请号：US11462115
申请日：2006-08-03
申请人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
发明人： Ravi K. Arimilli , Francis P. O'Connell , Hazim Shafi , Derek E. Williams , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译：数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。确定存储修改操作是否具有相关的旁路指示。响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。

5. 发明授权

US08949579B2 Ineffective prefetch determination and latency optimization 有权
标题翻译：无效的预取确定和延迟优化
公开(公告)号：US08949579B2
公开(公告)日：2015-02-03
申请号：US12897008
申请日：2010-10-04
申请人： Miles R. Dooley , Venkat R. Indukuru , Alex E. Mericas , Francis P. O'Connell
发明人： Miles R. Dooley , Venkat R. Indukuru , Alex E. Mericas , Francis P. O'Connell
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/383 , G06F12/0897 , G06F2212/6024
摘要： A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyzes the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the ineffectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.
摘要翻译：信息处理系统（IHS）的处理器在指令处理期间响应于需求负载启动L3高速缓存预取操作。处理器随机选择L3高速缓存预取作为目标预取指令进行跟踪。处理器发起L1高速缓存目标预取操作，并将所得到的目标预取指令存储在L1高速缓存中。如果需求负载到达，则处理器分析目标预取指令的有效性并确定预取数据的来源。如果请求没有到达，则处理器测试以确定特定预取指令是否在高速缓存中超时并且识别预取操作的无效。处理器随机抽取多个预取操作，并生成预取有效性和其他有用的预取信息的历史记录。处理器存储预取有效性信息以便能够减少或去除无效的预取操作。

6. 发明申请

US20130232320A1 PERSISTENT PREFETCH DATA STREAM SETTINGS 有权
标题翻译：数据预处理数据流设置
公开(公告)号：US20130232320A1
公开(公告)日：2013-09-05
申请号：US13410260
申请日：2012-03-01
申请人： JASON N. DALE , MILES R. DOOLEY , RICHARD J. EICKEMEYER , BRADLY G. FREY , YAOQING GAO , FRANCIS P. O'CONNELL , JEFFREY A. STUECHELI
发明人： JASON N. DALE , MILES R. DOOLEY , RICHARD J. EICKEMEYER , BRADLY G. FREY , YAOQING GAO , FRANCIS P. O'CONNELL , JEFFREY A. STUECHELI
IPC分类号： G06F15/82 , G06F9/312 , G06F9/30
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/6028
摘要： A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.
摘要翻译：预取单元包括一个过渡寄存器和一个长度寄存器。 Transient寄存器容纳数据流预取的瞬态指示。长度寄存器托管用于数据流预取的流长度的指示。预取单元监视临时寄存器和长度寄存器。当Transient寄存器指示瞬态时，预取单元产生具有直到流长度限制的瞬态特性的数据流的预取请求，并且长度寄存器指示数据流预取的流长度限制。与预取单元耦合的高速缓存控制器实现高速缓存替换策略和高速缓存一致性协议。高速缓存控制器将响应于预取请求的从存储器提供的数据写入高速缓存中，并显示瞬时信号。高速缓存控制器使高速缓存行受到与缓存替换策略无关的暂态指示。

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