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71. 发明授权

US07781273B2 Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure 有权
标题翻译：具有不同通道区域高度的多个翅片的半导体结构和形成半导体结构的方法
公开(公告)号：US07781273B2
公开(公告)日：2010-08-24
申请号：US12127033
申请日：2008-05-27
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338 , H01L21/337 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

72. 发明授权

US07348633B2 Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions 失效
标题翻译：具有一个或多个SOI区域和/或体半导体区域的混合晶体表面取向衬底
公开(公告)号：US07348633B2
公开(公告)日：2008-03-25
申请号：US11164345
申请日：2005-11-18
申请人： Junedong Lee , Devendra K. Sadana , Dominic J. Schepis , Ghavam G. Shahidi
发明人： Junedong Lee , Devendra K. Sadana , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L27/01 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76251 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/04
摘要： A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation. A surface of the single stack may further include a non-SOI region and/or at least one second SOI region. The non-SOI region may include bulk silicon that extends through all of the insulator layers of the single stack and has a thickness different than that of the first silicon layer. Each second SOI region has a second semiconductor layer having a thickness different than that of the first semiconductor layer and/or a different surface orientation than the first surface orientation. The substrate thus allows formation of different devices on optimal substrate regions that may include different surface orientations and/or different thicknesses and/or different bulk or SOI structures.
摘要翻译：公开了一种用于半导体器件的衬底，在一个实施例中，包括在单个堆叠中彼此结合的多个绝缘体上半导体（SOI）晶片。堆叠的远端包括具有厚度和第一表面取向的第一半导体层的第一SOI区域。单个堆叠的表面可以进一步包括非SOI区域和/或至少一个第二SOI区域。非SOI区域可以包括延伸穿过单个堆叠的所有绝缘体层并且具有与第一硅层的厚度不同的厚度的体硅。每个第二SOI区域具有与第一半导体层的厚度不同的第二半导体层和/或与第一表面取向不同的表面取向。因此，衬底允许在可以包括不同表面取向和/或不同厚度和/或不同的体或SOI结构的最佳衬底区域上形成不同的器件。

73. 发明授权

US07183573B2 Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet 失效
标题翻译：对称和非对称肖特基接触到SOI mosfet的一次性间隔物
公开(公告)号：US07183573B2
公开(公告)日：2007-02-27
申请号：US09978528
申请日：2001-10-17
申请人： Andres Bryant , Jerome B. Lasky , Effendi Leobandung , Dominic J. Schepis
发明人： Andres Bryant , Jerome B. Lasky , Effendi Leobandung , Dominic J. Schepis
IPC分类号： H01L21/00 , H01L21/238
CPC分类号： H01L29/66643 , H01L29/458 , H01L29/6653 , H01L29/66659 , H01L29/66772 , H01L29/7839 , H01L29/78609 , H01L29/78612 , H01L29/78621 , H01L29/78624 , H01L29/812
摘要： A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.
摘要翻译：公开了一种绝缘体上硅晶体管，其具有与身体的肖特基接触。肖特基接触可以形成在栅极导体的源极和/或漏极侧。在栅极导体的侧壁上形成有至少一部分是一次性的间隔物。延伸区域设置在衬底下延伸在间隔物和栅极导体之下。源极和漏极扩散区域被注入邻近延伸区域的衬底中。然后移除间隔件的一次性部分以暴露延伸区域的一部分。至少在延伸区域中形成金属层，导致肖特基接触。

74. 发明授权

US07115463B2 Patterning SOI with silicon mask to create box at different depths 失效
标题翻译：用硅掩模图案化SOI以在不同深度创建盒子
公开(公告)号：US07115463B2
公开(公告)日：2006-10-03
申请号：US10923246
申请日：2004-08-20
申请人： Devendra K. Sadana , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Devendra K. Sadana , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.
摘要翻译：本发明提供一种制造图案化的绝缘体上硅衬底的方法，其包括双重深度SOI区域或同一衬底内的SOI和非SOI区域。本发明的方法包括在含Si材料的表面上形成具有至少一个开口的硅掩模，通过使用蚀刻工艺使含Si材料通过至少一个开口凹陷，以提供具有至少一个凹部区域和非凹陷区域，并且在凹陷区域中形成第一掩埋绝缘区域和凹陷区域中的第二掩埋绝缘区域。根据本发明，非凹陷区域中的第一掩埋绝缘区域位于凹陷区域中的第二掩埋隔离区域的上方。可以采用剥离步骤去除第一掩埋绝缘区域和位于上方的材料，以提供包含SOI和非SOI区域的衬底。

75. 发明授权

US06891228B2 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture 失效
标题翻译：具有沉积的升高源极/漏极的超薄SOI上的CMOS器件及其制造方法
公开(公告)号：US06891228B2
公开(公告)日：2005-05-10
申请号：US10952286
申请日：2004-09-28
申请人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
发明人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/74 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/66772
摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅极电介质，在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 并且从所述注入层和所述SOI晶片听到所述器件以形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于比所述STI区域低的位置。

76. 发明授权

US06531375B1 Method of forming a body contact using BOX modification 失效
标题翻译：使用BOX修饰形成身体接触的方法
公开(公告)号：US06531375B1
公开(公告)日：2003-03-11
申请号：US09955375
申请日：2001-09-18
申请人： Kenneth J. Giewont , Eric Adler , Neena Garg , Michael J. Hargrove , Charles W. Koburger, III , Junedong Lee , Dominic J. Schepis , Isabel Ying Yang
发明人： Kenneth J. Giewont , Eric Adler , Neena Garg , Michael J. Hargrove , Charles W. Koburger, III , Junedong Lee , Dominic J. Schepis , Isabel Ying Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76267
摘要： A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.
摘要翻译：一种用于在SOI衬底上形成衬底接触区而不需要额外空间的新方法，并且为了提供较低的扩散电容。该方法利用已知的半导体处理技术。这种用于选择性地修改SOI衬底的BOX区域的方法包括首先提供硅衬底。然后，使用SIMOX技术（例如，O 2注入）离子注入基底。接下来，对基板进行光图案化以保护修改的BOX区域。然后，使用“接触式”O2注入进一步进行离子注入，从而得到通常实施的良好质量BOX。最后一步是退火基板。存在掩模的衬底的区域将不会接收“接触”O 2注入（第二离子注入），这反过来将导致泄漏BOX。

77. 发明授权

US06437377B1 Low dielectric constant sidewall spacer using notch gate process 失效
标题翻译：低介电常数侧壁间隔板采用切口浇口工艺
公开(公告)号：US06437377B1
公开(公告)日：2002-08-20
申请号：US09768525
申请日：2001-01-24
申请人： Atul C. Ajmera , Ka Hing (Samuel) Fung , Victor Ku , Dominic J. Schepis
发明人： Atul C. Ajmera , Ka Hing (Samuel) Fung , Victor Ku , Dominic J. Schepis
IPC分类号： H01L2710
CPC分类号： H01L29/4991 , H01L21/28114 , H01L21/28194 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/6656 , H01L29/6659
摘要： A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.
摘要翻译：缺口门MOS器件包括封装的低介电材料或封装的空气或在缺口栅极的底部的真空。由于栅极和源极/漏极之间的界面位置处的介电常数低，所以该位置处的电容损耗显着降低。

78. 发明授权

US06429488B2 Densely patterned silicon-on-insulator (SOI) region on a wafer 失效
标题翻译：在晶片上的密集图案化的绝缘体上硅（SOI）区域
公开(公告)号：US06429488B2
公开(公告)日：2002-08-06
申请号：US09791273
申请日：2001-02-22
申请人： Effendi Leobandung , Devendra K. Sadana , Dominic J. Schepis , Ghavam G. Shahidi
发明人： Effendi Leobandung , Devendra K. Sadana , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L2712
CPC分类号： H01L21/76264 , H01L21/762 , H01L21/76267 , H01L21/76275 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.
摘要翻译：一种在半导体器件中制造SOI区域和体区的工艺。该方法包括提供SOI结构。 SOI结构具有薄的硅层，位于薄硅层下面的掩埋绝缘氧化物层和位于掩埋绝缘氧化物层下面的硅衬底。接下来，在SOI结构的顶部上沉积氮化物层。通过选择性地蚀刻氮化物层的部分来暴露SOI结构。未蚀刻的氮化物层的部分形成SOI区域。通过选择性蚀刻暴露的SOI结构的剩余部分来暴露硅衬底。在暴露的硅衬底的顶部上生长外延层以形成体区。最终去除SOI结构之上的氮化物部分。

79. 发明授权

US5614440A Method of forming a thermally activated noise immune fuse 失效
标题翻译：形成热激活噪声免疫保险丝的方法
公开(公告)号：US5614440A
公开(公告)日：1997-03-25
申请号：US419778
申请日：1995-04-11
申请人： Raschid J. Bezama , Dominic J. Schepis , Krishna Seshan
发明人： Raschid J. Bezama , Dominic J. Schepis , Krishna Seshan
IPC分类号： H01H85/00 , H01H85/02 , H01H85/046 , H01H85/12 , H01L23/525 , H01L23/58 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10S148/055
摘要： A method of fabricating a noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.
摘要翻译：一种制造具有亚微米尺寸的噪声免疫熔丝的方法，其可以通过电和热同步事件来编程。熔丝包括彼此紧密相邻的一对熔丝链，热耦合形成该对的两个连接的导热和电绝缘材料层，以及用于通过提示第二连接件对能量传递进行栅极编程的装置通过耦合层在链路之间。通过组合热和电脉冲来执行编程功能，与单个元件熔断器相比，熔丝结构的可靠性大大提高。

80. 发明授权

US4960726A BiCMOS process 失效
标题翻译： BiCMOS工艺
公开(公告)号：US4960726A
公开(公告)日：1990-10-02
申请号：US424363
申请日：1989-10-19
申请人： John S. Lechaton , Dominic J. Schepis
发明人： John S. Lechaton , Dominic J. Schepis
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8249
摘要： A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.
摘要翻译：一种制造BiCMOS器件的方法包括提供包括第一和第二电隔离器件区域的半导体衬底。在第一器件区域上形成一层绝缘材料，并且一层导电材料在该器件上保形地形成。去除导电层的部分以在第二器件区域的表面上留下基极接触，并且在第一器件区域的表面上形成绝缘栅极接触。在具有在绝缘栅极下方的沟道的第一器件区域中形成FET。在具有接触基极触点的基极区域的第二器件区域中形成垂直双极晶体管。

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