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1. 发明授权

US09105775B2 Textured multi-junction solar cell and fabrication method 有权
标题翻译：纹理多结太阳能电池及其制造方法
公开(公告)号：US09105775B2
公开(公告)日：2015-08-11
申请号：US13535974
申请日：2012-06-28
申请人： Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0236 , H01L31/0352 , H01L31/0725
CPC分类号： H01L31/02363 , H01L31/03529 , H01L31/0725 , Y02E10/50
摘要： A multi-junction photovoltaic device includes a germanium layer having pyramidal shapes with (111) facets exposed to form a textured surface. A first p-n junction is formed on or over the textured surface. Another p-n junction is formed over the first p-n junction and following the textured surface.
摘要翻译：多结光伏器件包括具有金字塔形状的锗层，其具有暴露以形成纹理表面的（111）刻面。在纹理表面上或上方形成第一个p-n结。另一个p-n结形成在第一个p-n结上并跟随有纹理的表面。

2. 发明授权

US09059245B2 Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
标题翻译：具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底
公开(公告)号：US09059245B2
公开(公告)日：2015-06-16
申请号：US13483781
申请日：2012-05-30
申请人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76243
摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.
摘要翻译：提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

3. 发明授权

US08866227B2 Thin semiconductor-on-insulator MOSFET with co-integrated silicon, silicon germanium and silicon doped with carbon channels 有权
标题翻译：具有共同集成硅，硅锗和掺杂碳通道的硅的薄绝缘体MOSFET
公开(公告)号：US08866227B2
公开(公告)日：2014-10-21
申请号：US13607743
申请日：2012-09-09
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/84 , H01L21/77 , H01L27/092 , H01L21/02 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域以及掺杂有碳层的硅的第三器件区域。然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

4. 发明授权

US08766353B2 Tunnel field effect transistor 失效
标题翻译：隧道场效应晶体管
公开(公告)号：US08766353B2
公开(公告)日：2014-07-01
申请号：US13558518
申请日：2012-07-26
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.
摘要翻译：公开了一种以不对称隧道FET（TFET）为特征的FET器件。 TFET包括栅极堆叠，栅极堆叠下方的沟道区域，邻接栅极叠层的第一和第二结，并且能够与沟道电连接。第一接头和第二接头具有不同的导电类型。 TFET还包括间隔物结构，使得栅极叠层的一侧上的间隔物形成比另一侧更薄。

5. 发明授权

US08659066B2 Integrated circuit with a thin body field effect transistor and capacitor 有权
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08659066B2
公开(公告)日：2014-02-25
申请号：US13345266
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/06
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
摘要翻译：集成电路包括晶体管和电容器。晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。栅堆叠包括金属层和第一高k电介质层。栅极间隔物位于栅极叠层的侧壁上。第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。第一硅化物区域位于第一源极/漏极区域上。第二硅化物区域位于第二源极/漏极区域上。电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。第二高k电介质层位于硅化物区域上。第二端子包括位于第二高k电介质层上的金属层。

6. 发明申请

US20140000687A1 TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD 有权
标题翻译：纹理多重太阳能电池和制造方法
公开(公告)号：US20140000687A1
公开(公告)日：2014-01-02
申请号：US13535974
申请日：2012-06-28
申请人： Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0236
CPC分类号： H01L31/02363 , H01L31/03529 , H01L31/0725 , Y02E10/50
摘要： A multi-junction photovoltaic device includes a germanium layer having pyramidal shapes with (111) facets exposed to form a textured surface. A first p-n junction is formed on or over the textured surface. Another p-n junction is formed over the first p-n junction and following the textured surface.
摘要翻译：多结光伏器件包括具有金字塔形状的锗层，其具有暴露以形成纹理表面的（111）刻面。在纹理表面上或上方形成第一个p-n结。另一个p-n结形成在第一个p-n结上并跟随有纹理的表面。

7. 发明授权

US08618554B2 Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide 有权
标题翻译：减少具有薄埋层氧化物的极薄SOI（ETSOI）层的接地面中毒的方法
公开(公告)号：US08618554B2
公开(公告)日：2013-12-31
申请号：US12941771
申请日：2010-11-08
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/15
CPC分类号： H01L29/78603 , H01L21/76254
摘要： The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.
摘要翻译：涉及超薄体BOX和双BOX完全耗尽的SOI器件的本公开内容，以及制造这些器件的方法，其具有外延扩散延迟半导体层，其减缓掺杂剂扩散到SOI沟道中。具有在衬底和SOI沟道之间的外延扩散延迟半导体层的本公开的器件的SOI沟道中的掺杂剂浓度比在没有外延扩散延迟半导体层的器件的SOI沟道中测量的掺杂剂浓度大约小50倍。

8. 发明申请

US20130341770A1 RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME 有权
标题翻译：辐射硬化SOI结构及其制备方法
公开(公告)号：US20130341770A1
公开(公告)日：2013-12-26
申请号：US13555271
申请日：2012-07-23
申请人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L29/02
CPC分类号： H01L21/31155 , H01L21/304 , H01L21/7624
摘要： An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.
摘要翻译：首先提供包括位于基底基板和顶部半导体有源层之间的掩埋绝缘体层的SOI衬底。然后可以在顶部半导体有源层的一部分上和/或内部形成半导体器件。掩埋绝缘体层的与埋入绝缘体层的与顶部半导体活性层形成界面的最上表面相对的最底表面可以暴露。然后，离子可以通过掩埋绝缘体层的最底部的表面注入埋入的绝缘体层的一部分中。将离子注入到不会干扰埋入的绝缘体层/顶部半导体有源层界面的能量范围内，同时在掩埋的绝缘体层/顶部半导体活性层界面附近保留相当薄的部分隐埋绝缘体层。

9. 发明申请

US20130320483A1 SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES 有权
标题翻译：半导体绝缘体（SOI）衬底，具有超薄SOI层和铜氧化物
公开(公告)号：US20130320483A1
公开(公告)日：2013-12-05
申请号：US13483781
申请日：2012-05-30
申请人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76243
摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.
摘要翻译：提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

10. 发明授权

US08574970B2 Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain 有权
标题翻译：形成具有阶梯状凸起源极/漏极的极薄半导体绝缘体（ETSOI）FET的方法
公开(公告)号：US08574970B2
公开(公告)日：2013-11-05
申请号：US12882490
申请日：2010-09-15
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/84
CPC分类号： H01L29/78654 , H01L29/66628 , H01L29/66772
摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.
摘要翻译：在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。还提供了形成上述MOSFET器件的方法。

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