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1. 发明申请

US20080224258A1 SEMICONDUCTOR STRUCTUE WITH MULTIPLE FINS HAVING DIFFERENT CHANNEL REGION HEIGHTS AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE 有权
标题翻译：具有不同通道区域的多个FINS的半导体结构和形成半导体结构的方法
公开(公告)号：US20080224258A1
公开(公告)日：2008-09-18
申请号：US12127033
申请日：2008-05-27
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/764
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并且具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

2. 发明授权

US07544994B2 Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure 有权
标题翻译：具有不同通道区域高度的多个翅片的半导体结构和形成半导体结构的方法
公开(公告)号：US07544994B2
公开(公告)日：2009-06-09
申请号：US11556844
申请日：2006-11-06
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

3. 发明申请

US20080122013A1 SEMICONDUCTOR STRUCTURE WITH MULTIPLE FINS HAVING DIFFERENT CHANNEL REGION HEIGHTS AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE 有权
标题翻译：具有不同通道区域的多个FINS的半导体结构和形成半导体结构的方法
公开(公告)号：US20080122013A1
公开(公告)日：2008-05-29
申请号：US11556844
申请日：2006-11-06
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并且具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

4. 发明授权

US07781273B2 Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure 有权
标题翻译：具有不同通道区域高度的多个翅片的半导体结构和形成半导体结构的方法
公开(公告)号：US07781273B2
公开(公告)日：2010-08-24
申请号：US12127033
申请日：2008-05-27
申请人： Dominic J. Schepis , Huilong Zhu
发明人： Dominic J. Schepis , Huilong Zhu
IPC分类号： H01L21/00 , H01L21/84 , H01L21/338 , H01L21/337 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.
摘要翻译：公开了具有翅片的半导体结构的实施例，翅片位于晶片的同一平面上并具有不同高度的沟道区。在一个实施例中，通过改变不同翅片的整体高度来实现不同的通道区域高度。在另一个实施例中，不同通道区域的高度是通过改变而不是不同翅片的整体高度来实现的，而是通过改变每个翅片内的半导体层的高度来实现。所公开的半导体结构实施例允许具有不同有效沟道宽度的不同的多门非平面FET（即，三栅极或双栅极FET）由相同的晶片形成，并且因此允许在包含多个FET（例如，静态随机存取存储器（SRAM）单元）被选择性地调整。

5. 发明授权

US10068990B2 Method of manufacturing MOS transistor with stack of cascaded nanowires 有权
公开(公告)号：US10068990B2
公开(公告)日：2018-09-04
申请号：US14387830
申请日：2013-08-06
申请人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
发明人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/423
摘要： A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

6. 发明授权

US09576802B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09576802B2
公开(公告)日：2017-02-21
申请号：US14412173
申请日：2012-07-19
申请人： Haizhou Yin , Huilong Zhu , Keke Zhang
发明人： Haizhou Yin , Huilong Zhu , Keke Zhang
IPC分类号： H01L21/331 , H01L21/28 , H01L29/66 , H01L21/3105 , H01L29/78 , H01L29/423 , H01L29/417
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/31051 , H01L29/41783 , H01L29/42376 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

7. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

8. 发明授权

US09252280B2 MOSFET and method for manufacturing the same 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US09252280B2
公开(公告)日：2016-02-02
申请号：US13510461
申请日：2011-11-18
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/66742 , H01L29/78609
摘要： The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.
摘要翻译：本公开公开了一种金属氧化物半导体场效应晶体管（MOSFET）及其制造方法。所述MOSFET包括：绝缘体上硅（SOI）晶片，其包含半导体衬底，掩埋绝缘层和半导体层，所述掩埋绝缘层位于所述半导体衬底上，所述半导体层位于所述掩埋绝缘层上; 半导体层上的栅极堆叠; 源极区域和漏极区域，其位于半导体层中并且在栅极堆叠的相对侧上; 以及沟道区，其位于所述半导体层中并且被所述源极区和所述漏极区夹持，其中所述MOSFET还包括背栅极，所述后栅极位于所述半导体衬底中，并且在所述半导体衬底的下部具有第一掺杂区域的背栅极和在后栅极的上部中的第二掺杂区域。

9. 发明申请

US20150311319A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150311319A1
公开(公告)日：2015-10-29
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

10. 发明申请

US20150221769A1 FINFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： FINFET及其制造方法
公开(公告)号：US20150221769A1
公开(公告)日：2015-08-06
申请号：US14419833
申请日：2012-08-24
申请人： Huilong Zhu , Miao Xu
发明人： Huilong Zhu , Miao Xu
IPC分类号： H01L29/78 , H01L21/3065 , H01L29/06 , H01L21/308 , H01L29/66 , H01L29/161
CPC分类号： H01L29/7849 , H01L21/3065 , H01L21/308 , H01L29/0611 , H01L29/0649 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7846 , H01L29/785
摘要： An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括：半导体衬底; 半导体衬底上的应力层; 在所述应力层上的半导体鳍片，所述半导体鳍片具有在其长度方向上延伸的两个侧壁; 半导体鳍片的侧壁上的栅极电介质; 栅极电介质上的栅极导体; 以及半导体鳍片的两端的源极区域和漏极区域，其中应力层在半导体鳍片的下方并且平行地延伸，并且在半导体鳍片的长度方向上对半导体鳍片施加应力。

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