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1. 发明申请

US20080022237A1 DEVICE MODELING FOR PROXIMITY EFFECTS 审中-公开
标题翻译：近似效应的设备建模
公开(公告)号：US20080022237A1
公开(公告)日：2008-01-24
申请号：US11866796
申请日：2007-10-03
申请人： Eric Adler , Serge Biesemans , Micah Galland , Terence Hook , Judith McCullen , Eric Phipps , James Slinkman
发明人： Eric Adler , Serge Biesemans , Micah Galland , Terence Hook , Judith McCullen , Eric Phipps , James Slinkman
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G06F17/5036 , G06F17/5068
摘要： A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.
摘要翻译：一种用于校正由相邻结构施加的变量的给定感兴趣结构的软件模型的方法。首先确定相邻结构施加的变量的空间范围。然后为空间范围分配一个值，该空间范围随着从相邻结构到给定结构的距离的函数而变化。最后，将该值附加到给定结构的模型中。

2. 发明授权

US07302376B2 Device modeling for proximity effects 有权
标题翻译：邻近效应的设备建模
公开(公告)号：US07302376B2
公开(公告)日：2007-11-27
申请号：US10248853
申请日：2003-02-25
申请人： Eric Adler , Serge Biesemans , Micah S. Galland , Terence B. Hook , Judith H. McCullen , Eric S. Phipps , James A. Slinkman
发明人： Eric Adler , Serge Biesemans , Micah S. Galland , Terence B. Hook , Judith H. McCullen , Eric S. Phipps , James A. Slinkman
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G06F17/5036 , G06F17/5068
摘要： A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.
摘要翻译：一种用于校正由相邻结构施加的变量的给定感兴趣结构的软件模型的方法。首先确定相邻结构施加的变量的空间范围。然后为空间范围分配一个值，该空间范围随着从相邻结构到给定结构的距离的函数而变化。最后，将该值附加到给定结构的模型中。

3. 发明申请

US20050189615A1 NON-CONTINUOUS ENCAPSULATION LAYER FOR MIM CAPACITOR 有权
标题翻译： MIM电容器的非连续封装层
公开(公告)号：US20050189615A1
公开(公告)日：2005-09-01
申请号：US10908491
申请日：2005-05-13
申请人： Wagdi Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara Waterhouse , Michael Zierak
发明人： Wagdi Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara Waterhouse , Michael Zierak
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/57
摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.
摘要翻译：本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

4. 发明授权

US06770907B2 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
标题翻译：基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法
公开(公告)号：US06770907B2
公开(公告)日：2004-08-03
申请号：US10449426
申请日：2003-05-30
申请人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
发明人： Wagdi W. Abadeer , Eric Adler , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jonathan M. McKenna , Jed H. Rankin , Edward W. Sengle , William R. Tonti
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.
摘要翻译：一种检测半导体工艺应力诱发缺陷的方法。该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管。 DRAM单元可以代替二极管。还公开了使用二极管作为反熔丝。

5. 发明授权

US06683345B1 Semiconductor device and method for making the device having an electrically modulated conduction channel 有权
标题翻译：用于制造具有电调制传导通道的器件的半导体器件和方法
公开(公告)号：US06683345B1
公开(公告)日：2004-01-27
申请号：US09467537
申请日：1999-12-20
申请人： Eric Adler , James S. Dunn , Joseph Iadanza , Jenifer E. Lary , Kent E. Morrett , Josef S. Watts
发明人： Eric Adler , James S. Dunn , Joseph Iadanza , Jenifer E. Lary , Kent E. Morrett , Josef S. Watts
IPC分类号： H01L2976
CPC分类号： H01L29/8605 , H01L21/823412 , H01L21/823481 , H01L27/0802 , H01L29/78 , H03M1/0604 , H03M1/66
摘要： A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.
摘要翻译：具有电调制的导电通道的半导体器件。在包围扩散区域的衬底内形成沟槽结构。沟槽结构将形成在扩散区域内的器件与衬底的剩余部分隔离。沟壁被制成足够薄，使得扩散区域内的通道的宽度可以通过在沟槽壁和衬底之间施加电势来控制。形成在沟槽结构内的晶体管具有由所施加的电压控制的导通沟道宽度，允许晶体管的增益与衬底上的其它晶体管的增益匹配。

6. 发明授权

US06531375B1 Method of forming a body contact using BOX modification 失效
标题翻译：使用BOX修饰形成身体接触的方法
公开(公告)号：US06531375B1
公开(公告)日：2003-03-11
申请号：US09955375
申请日：2001-09-18
申请人： Kenneth J. Giewont , Eric Adler , Neena Garg , Michael J. Hargrove , Charles W. Koburger, III , Junedong Lee , Dominic J. Schepis , Isabel Ying Yang
发明人： Kenneth J. Giewont , Eric Adler , Neena Garg , Michael J. Hargrove , Charles W. Koburger, III , Junedong Lee , Dominic J. Schepis , Isabel Ying Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76267
摘要： A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.
摘要翻译：一种用于在SOI衬底上形成衬底接触区而不需要额外空间的新方法，并且为了提供较低的扩散电容。该方法利用已知的半导体处理技术。这种用于选择性地修改SOI衬底的BOX区域的方法包括首先提供硅衬底。然后，使用SIMOX技术（例如，O 2注入）离子注入基底。接下来，对基板进行光图案化以保护修改的BOX区域。然后，使用“接触式”O2注入进一步进行离子注入，从而得到通常实施的良好质量BOX。最后一步是退火基板。存在掩模的衬底的区域将不会接收“接触”O 2注入（第二离子注入），这反过来将导致泄漏BOX。

7. 发明授权

US5757050A Field effect transistor having contact layer of transistor gate electrode material 失效
标题翻译：场效应晶体管具有晶体管栅电极材料的接触层
公开(公告)号：US5757050A
公开(公告)日：1998-05-26
申请号：US823360
申请日：1997-03-24
申请人： Eric Adler , Subhash Balakrishna Kulkarni , Randy William Mann , Werner Alois Rausch , Luigi Ternullo, Jr.
发明人： Eric Adler , Subhash Balakrishna Kulkarni , Randy William Mann , Werner Alois Rausch , Luigi Ternullo, Jr.
IPC分类号： H01L27/06 , H01L27/11 , H01L27/12 , H01L27/01
CPC分类号： H01L27/1203 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described. Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.
摘要翻译：描述了改进的场效应晶体管（FET）结构。它们包括薄膜晶体管（TFT），其中接触层将TFT的扩散区域直接连接到另一个器件（例如另一晶体管）的有源部位。本发明特别适用于建立在一个或多个导电柱上的TFT。还描述了并入TFT中的一个或多个的静态随机存取存储器（SRAM）单元。此外，本发明涉及用于防止或减轻在形成接触层期间与气刨相关的问题的方法。

8. 发明授权

US5744384A Semiconductor structures which incorporate thin film transistors 失效
标题翻译：掺入薄膜晶体管的半导体结构
公开(公告)号：US5744384A
公开(公告)日：1998-04-28
申请号：US716001
申请日：1996-09-19
申请人： Eric Adler , Subhash Balakrishna Kulkarni , Randy William Mann , Werner Alois Rausch , Luigi Ternullo, Jr.
发明人： Eric Adler , Subhash Balakrishna Kulkarni , Randy William Mann , Werner Alois Rausch , Luigi Ternullo, Jr.
IPC分类号： H01L27/06 , H01L27/11 , H01L27/12 , H01L21/00
CPC分类号： H01L27/1203 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described. Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.
摘要翻译：描述了改进的场效应晶体管（FET）结构。它们包括薄膜晶体管（TFT），其中接触层将TFT的扩散区域直接连接到另一个器件（例如另一晶体管）的有源部位。本发明特别适用于建立在一个或多个导电柱上的TFT。还描述了并入TFT中的一个或多个的静态随机存取存储器（SRAM）单元。此外，本发明涉及用于防止或减轻在形成接触层期间与气刨相关的问题的方法。

9. 发明授权

US5670812A Field effect transistor having contact layer of transistor gate electrode material 失效
标题翻译：场效应晶体管具有晶体管栅电极材料的接触层
公开(公告)号：US5670812A
公开(公告)日：1997-09-23
申请号：US536725
申请日：1995-09-29
申请人： Eric Adler , Subhash Balakrishna Kulkarni , Randy William Mann , Werner Alois Rausch , Luigi Ternullo, Jr.
发明人： Eric Adler , Subhash Balakrishna Kulkarni , Randy William Mann , Werner Alois Rausch , Luigi Ternullo, Jr.
IPC分类号： H01L27/06 , H01L27/11 , H01L27/12 , H01L27/01
CPC分类号： H01L27/1203 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described. Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.
摘要翻译：描述了改进的场效应晶体管（FET）结构。它们包括薄膜晶体管（TFT），其中接触层将TFT的扩散区域直接连接到另一个器件（例如另一晶体管）的有源部位。本发明特别适用于建立在一个或多个导电柱上的TFT。还描述了并入TFT中的一个或多个的静态随机存取存储器（SRAM）单元。此外，本发明涉及用于防止或减轻在形成接触层期间与气刨相关的问题的方法。

10. 发明授权

US5521118A Sidewall strap 失效
标题翻译：侧壁带
公开(公告)号：US5521118A
公开(公告)日：1996-05-28
申请号：US440574
申请日：1995-05-15
申请人： Chung H. Lam , James S. Nakos , Donald M. Kenney , Eric Adler
发明人： Chung H. Lam , James S. Nakos , Donald M. Kenney , Eric Adler
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/283
CPC分类号： H01L27/10861 , H01L21/76897 , H01L23/485 , H01L2924/0002 , Y10S257/90
摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.
摘要翻译：本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。侧壁连接器具有包括外表面的顶部部分。导电构件接触顶部，将轨道连接到导电区域或外部导体。位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。连接器用于形成用于DRAM单元的带子。

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