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1. 发明授权

US07115463B2 Patterning SOI with silicon mask to create box at different depths 失效
标题翻译：用硅掩模图案化SOI以在不同深度创建盒子
公开(公告)号：US07115463B2
公开(公告)日：2006-10-03
申请号：US10923246
申请日：2004-08-20
申请人： Devendra K. Sadana , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Devendra K. Sadana , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.
摘要翻译：本发明提供一种制造图案化的绝缘体上硅衬底的方法，其包括双重深度SOI区域或同一衬底内的SOI和非SOI区域。本发明的方法包括在含Si材料的表面上形成具有至少一个开口的硅掩模，通过使用蚀刻工艺使含Si材料通过至少一个开口凹陷，以提供具有至少一个凹部区域和非凹陷区域，并且在凹陷区域中形成第一掩埋绝缘区域和凹陷区域中的第二掩埋绝缘区域。根据本发明，非凹陷区域中的第一掩埋绝缘区域位于凹陷区域中的第二掩埋隔离区域的上方。可以采用剥离步骤去除第一掩埋绝缘区域和位于上方的材料，以提供包含SOI和非SOI区域的衬底。

2. 发明授权

US08232186B2 Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure 失效
标题翻译：在PFET上对NFET和SiGe沟道反向eSiGe进行积分的方法及相关结构
公开(公告)号：US08232186B2
公开(公告)日：2012-07-31
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L21/20
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

3. 发明申请

US20120228716A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 审中-公开
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20120228716A1
公开(公告)日：2012-09-13
申请号：US13478400
申请日：2012-05-23
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.
摘要翻译：包括在NFET的沟道中具有嵌入硅锗（SiGe）插头的NFET的结构; 具有SiGe沟道的PFET; 以及在NFET和PFET之间的沟槽隔离，其中NFET和PFET没有SiGe外延生长边缘效应。

4. 发明授权

US06900092B2 Surface engineering to prevent epi growth on gate poly during selective epi processing 失效
标题翻译：表面工程，以防止在选择性epi处理期间在栅极poly上的epi生长
公开(公告)号：US06900092B2
公开(公告)日：2005-05-31
申请号：US10183336
申请日：2002-06-27
申请人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21/20 , H01L21/336 , H01L29/78 , H01L21/8238 , H01L21/31 , H01L21/3205
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02639 , H01L29/66628 , Y10S438/976
摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
摘要翻译：本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

5. 发明授权

US06440807B1 Surface engineering to prevent EPI growth on gate poly during selective EPI processing 有权
标题翻译：表面工程，以防止EPI在选择性EPI加工过程中对聚酰胺的生长
公开(公告)号：US06440807B1
公开(公告)日：2002-08-27
申请号：US09882095
申请日：2001-06-15
申请人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
发明人： Atul C. Ajmera , Dominic J. Schepis , Michael D. Steigerwalt
IPC分类号： H01L21336
CPC分类号： H01L29/7834 , H01L21/02532 , H01L21/02639 , H01L29/66628 , Y10S438/976
摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
摘要翻译：本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

6. 发明申请

US20090294801A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 失效
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20090294801A1
公开(公告)日：2009-12-03
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092 , H01L21/205 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

7. 发明申请

US20080261371A1 VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION 有权
标题翻译：具有主要载体累积层的垂直双极晶体管，作为用于SOI BiCMOS的半导体器件，具有减少的基底氧化物厚度用于低基板偏压运行
公开(公告)号：US20080261371A1
公开(公告)日：2008-10-23
申请号：US12144998
申请日：2008-06-24
申请人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66265
摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.
摘要翻译：本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。还提供了背栅CMOS装置。

8. 发明授权

US07394131B2 STI formation in semiconductor device including SOI and bulk silicon regions 有权
标题翻译：在包括SOI和体硅区域的半导体器件中形成STI
公开(公告)号：US07394131B2
公开(公告)日：2008-07-01
申请号：US11425467
申请日：2006-06-21
申请人： Michael D. Steigerwalt , Mahender Kumar , Herbert L. Ho , David M. Dobuzinsky , Johnathan E. Faltermeier , Denise Pendleton
发明人： Michael D. Steigerwalt , Mahender Kumar , Herbert L. Ho , David M. Dobuzinsky , Johnathan E. Faltermeier , Denise Pendleton
IPC分类号： H01L27/01
CPC分类号： H01L21/7624 , H01L21/3081 , H01L21/31612 , H01L21/76283
摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.
摘要翻译：公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻，并蚀刻穿过SOI区域的埋层绝缘体。用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

9. 发明授权

US06964897B2 SOI trench capacitor cell incorporating a low-leakage floating body array transistor 有权
标题翻译：掺有低泄漏浮体阵列晶体管的SOI沟槽电容器单元
公开(公告)号：US06964897B2
公开(公告)日：2005-11-15
申请号：US10250157
申请日：2003-06-09
申请人： Karen A. Bard , David M. Dobuzinsky , Herbert L. Ho , Mahendar Kumar , Denise Pendleton , Michael D. Steigerwalt , Brian L. Walsh
发明人： Karen A. Bard , David M. Dobuzinsky , Herbert L. Ho , Mahendar Kumar , Denise Pendleton , Michael D. Steigerwalt , Brian L. Walsh
IPC分类号： H01L21/77 , H01L21/334 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/7841
摘要： A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.
摘要翻译：在整个阵列中延伸的具有均匀BOX层的SOI晶片中的DRAM阵列消除了处理中的环氧化物步骤; 将掩埋板与植入物连接，该植入物又连接到延伸穿过设备层的导电插塞和被偏置在地面上的盒子; 而通过晶体管是具有浮动体的平面NFET，其具有通过接地位线接地的泄漏放电路径。

10. 发明申请

US20110298008A1 SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：自对准嵌入式SiGe结构及其制造方法
公开(公告)号：US20110298008A1
公开(公告)日：2011-12-08
申请号：US12795683
申请日：2010-06-08
申请人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
发明人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/3247 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7848
摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
摘要翻译：低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

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