专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080251814A1 HETERO-BONDED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH AN UNPINNING DIELECTRIC LAYER 审中-公开
标题翻译：带绝缘介质层的绝缘半导体绝缘体衬底
公开(公告)号：US20080251814A1
公开(公告)日：2008-10-16
申请号：US11735724
申请日：2007-04-16
申请人： Byoung H. Lee
发明人： Byoung H. Lee
IPC分类号： H01L29/737 , H01L21/44
CPC分类号： H01L21/76254
摘要： A hetero-bonded SOI substrate comprises a stack of a semiconductor handle substrate, an isolation insulator layer, a depinning dielectric layer, and a top non-silicon semiconductor layer. The depinning layer abuts both the top non-silicon semiconductor layer and the isolation insulator layer and relaxes Fermi level pinning in the top non-silicon semiconductor layer. The top non-silicon semiconductor layer may be a III-V compound semiconductor layer such as GaAs and the depinning dielectric layer may be a (GdxGa1-x)2O3 layer. The interface defect density may be reduced below 5.0×1011 cm−2 eV−1.
摘要翻译：异质结的SOI衬底包括半导体处理衬底，隔离绝缘体层，去铝电介质层和顶部非硅半导体层的叠层。脱模层邻接顶部非硅半导体层和隔离绝缘体层，并且松弛顶部非硅半导体层中的费米能级钉扎。顶部非硅半导体层可以是诸如GaAs的III-V化合物半导体层，并且去电介质层可以是（Gd x Ga 1-x N） SUB> 2 3 层。界面缺陷密度可以降低到低于5.0×10 12 cm -2 eV -1 -1。

2. 发明授权

US06891228B2 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture 失效
标题翻译：具有沉积的升高源极/漏极的超薄SOI上的CMOS器件及其制造方法
公开(公告)号：US06891228B2
公开(公告)日：2005-05-10
申请号：US10952286
申请日：2004-09-28
申请人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
发明人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/74 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/66772
摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅极电介质，在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 并且从所述注入层和所述SOI晶片听到所述器件以形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于比所述STI区域低的位置。

3. 发明申请

US20120256270A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 审中-公开
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20120256270A1
公开(公告)日：2012-10-11
申请号：US13525840
申请日：2012-06-18
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

4. 发明申请

US20090294867A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 失效
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20090294867A1
公开(公告)日：2009-12-03
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

5. 发明授权

US08236686B2 Dual metal gates using one metal to alter work function of another metal 失效
标题翻译：双金属门使用一种金属来改变另一种金属的功能
公开(公告)号：US08236686B2
公开(公告)日：2012-08-07
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

6. 发明授权

US06828630B2 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture 失效
标题翻译：具有沉积的升高源极/漏极的超薄SOI上的CMOS器件及其制造方法
公开(公告)号：US06828630B2
公开(公告)日：2004-12-07
申请号：US10338103
申请日：2003-01-07
申请人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
发明人： Heemyong Park , Byoung H. Lee , Paul D. Agnello , Dominic J. Schepis , Ghavam G. Shahidi
IPC分类号： H01L2976
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/66772
摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。

7. 发明授权

US06746924B1 Method of forming asymmetric extension mosfet using a drain side spacer 失效
标题翻译：使用排水侧间隔物形成不对称延伸mosfet的方法
公开(公告)号：US06746924B1
公开(公告)日：2004-06-08
申请号：US10248884
申请日：2003-02-27
申请人： Byoung H. Lee , Anda C. Mocuta
发明人： Byoung H. Lee , Anda C. Mocuta
IPC分类号： H01L21335
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823425 , H01L21/823468 , H01L29/665 , H01L29/7835
摘要： A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. A photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor. Then damaged portions of the nitride layer are removed while leaving undamaged portions of the nitride layer as a nitride mask to protect at least a portion of each drain region and at least one gate sidewall from a subsequent dopant implant, which is performed into the source regions and the drain regions while using the undamaged portions of the nitride layer as a mask to form the asymmetric extension MOSFET device. In some embodiments the nitride mask can be etched to form drain side spacers to provide different spacings for the source and drain extension ion implants.
摘要翻译：使用漏极侧间隔物形成不对称扩展MOSFET的方法，其允许为每个单独的MOSFET器件选择源极和漏极侧，并且还允许源极和漏极延伸注入剂量的独立设计或调谐以及其与门。在每个漏极区域的至少一部分上形成光致抗蚀剂掩模，随后是成角度的离子注入，在该离子注入期间，光致抗蚀剂掩模和栅极导体在氮化物层的至少一部分和漏极区域的至少一个侧壁上屏蔽氮化物层门导体不受角度离子注入的损伤，其选择性地损坏未被光致抗蚀剂掩模和栅极导体保护的氮化物层的部分。然后去除氮化物层的损坏部分，同时留下氮化物层的未损坏部分作为氮化物掩模，以保护每个漏极区域的至少一部分和至少一个栅极侧壁与随后的掺杂剂注入，其进行到源极区域和漏极区域，同时使用氮化物层的未损坏部分作为掩模来形成非对称扩展MOSFET器件。在一些实施例中，可以蚀刻氮化物掩模以形成漏极侧间隔物，以为源极和漏极延伸离子植入物提供不同的间隔。

8. 发明授权

US06653698B2 Integration of dual workfunction metal gate CMOS devices 有权
公开(公告)号：US06653698B2
公开(公告)日：2003-11-25
申请号：US10034009
申请日：2001-12-20
申请人： Byoung H. Lee , Effendi Leobandung , Ghavam G. Shahidi
发明人： Byoung H. Lee , Effendi Leobandung , Ghavam G. Shahidi
IPC分类号： H01L2976
CPC分类号： H01L27/1203 , H01L21/823842 , H01L21/823857 , H01L21/84
摘要： A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, VT. Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired VT into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式