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71. 发明授权

US07893519B2 Integrated circuit with conductive structures 有权
标题翻译：具有导电结构的集成电路
公开(公告)号：US07893519B2
公开(公告)日：2011-02-22
申请号：US12128336
申请日：2008-05-28
申请人： Franz Hofmann
发明人： Franz Hofmann
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L27/11524
摘要： An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.
摘要翻译：集成电路包括晶体管阵列和多个字线，其中字线中的单个字线与阵列中的多个晶体管耦合。与字线绝缘的导电结构被布置在字线下方的层中，并且布置在晶体管之间。

72. 发明授权

US07767567B2 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US07767567B2
公开(公告)日：2010-08-03
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/3205
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

73. 发明申请

US20080096352A1 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US20080096352A1
公开(公告)日：2008-04-24
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

74. 发明授权

US07307865B2 Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权
标题翻译：集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法
公开(公告)号：US07307865B2
公开(公告)日：2007-12-11
申请号：US10505320
申请日：2003-02-17
申请人： Franz Hofmann , Richard Johannes Luyken , Till Schlosser
发明人： Franz Hofmann , Richard Johannes Luyken , Till Schlosser
IPC分类号： G11C17/00
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译：具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。该层可以应用在后端进程中。

75. 发明授权

US07154138B2 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement 失效
标题翻译：晶体管布置，用于操作晶体管布置作为数据存储元件的方法和用于产生晶体管布置的方法
公开(公告)号：US07154138B2
公开(公告)日：2006-12-26
申请号：US10481278
申请日：2002-06-20
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11553 , H01L29/66833 , H01L29/7923
摘要： The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter, and, in between, a channel region, and also a gate region beside the channel region and, in between, an electrically insulating layer sequence, wherein two mutually spatially separate sections of the electrically insulating layer sequence in each case serve for the storage of charge carriers.
摘要翻译：本发明涉及具有衬底和垂直晶体管的晶体管装置，其包括：第一电极区域，基本上在其上方布置的第二电极区域，以及沟道区域之间以及沟道区域旁边的栅极区域，以及之间，电绝缘层序列，其中电绝缘层序列的两个相互空间分离的部分在每种情况下用于存储电荷载体。

76. 发明申请

US20060022248A1 Electronic data memory device for a high read current 审中-公开
标题翻译：用于高读取电流的电子数据存储器件
公开(公告)号：US20060022248A1
公开(公告)日：2006-02-02
申请号：US11167386
申请日：2005-06-27
申请人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
发明人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10873 , H01L29/7851
摘要： Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).
摘要翻译：用于高读取电流的电子数据存储器件本发明提供一种布置在衬底（401）上并具有至少一个存储单元（100）的存储器件。存储单元包括用于存储电荷的存储电容器（200）晶体管（300），用于选择存储单元（100）。选择晶体管包括第一导电电极（301），第二导电电极（302）和控制电极（303），控制电极（303）由栅极单元（400）提供，栅极单元（400）具有从基板（401），其被栅极氧化物层（406）和栅极电极层（403）包围，使得第一和第二栅极元件（408a，408b）设置在第一和第二栅极元件（408a，408b）的相对侧向区域所述翅片（405），第三栅极元件（408c）设置在所述鳍状物（405）的与所述基板（401）的表面平行的区域。

77. 发明申请

US20050201187A1 Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权
标题翻译：集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法
公开(公告)号：US20050201187A1
公开(公告)日：2005-09-15
申请号：US10505320
申请日：2003-02-17
申请人： Franz Hofmann , Richard Luyken , Till Schlosser
发明人： Franz Hofmann , Richard Luyken , Till Schlosser
IPC分类号： H01L27/10 , G11C8/02 , G11C16/02 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L27/24 , H01L27/28
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译：具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。该层可以应用在后端进程中。

78. 发明申请

US20050100938A1 Vertical impedance sensor arrangement and method for producing a vertical impedance sensor arrangement 审中-公开
标题翻译：垂直阻抗传感器布置和垂直阻抗传感器布置方法
公开(公告)号：US20050100938A1
公开(公告)日：2005-05-12
申请号：US10939319
申请日：2004-09-09
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
IPC分类号： C12Q1/68 , G01N33/543
CPC分类号： G01N33/54386 , G01N27/3276
摘要： Vertical impedance sensor arrangement including a substrate, a first electrically conductive structure having a first uncovered surface and being arranged in and/or on the substrate, a spacer arranged above the substrate and/or at least partially on the first electrically conductive structure, a second electrically conductive structure having a second uncovered surface and being arranged on the spacer, and capture molecules, which are immobilized on the first and on the second uncovered surface, are set up such that particles to be detected hybridize with the capture molecules. The spacer is formed separately from the substrate, and the thickness of the spacer is defined by means of a deposition method.
摘要翻译：垂直阻抗传感器布置包括基底，具有第一未覆盖表面并布置在基底中和/或基底上的第一导电结构，布置在基底上和/或至少部分地在第一导电结构上的间隔物，第二具有第二未覆盖表面并布置在间隔物上的导电结构，并且被固定在第一和第二未覆盖表面上的捕获分子被设置成使得待检测的颗粒与捕获分子杂交。间隔物与衬底分开形成，并且通过沉积方法限定间隔物的厚度。

79. 发明申请

US20050032311A1 Fabrication method for memory cell 失效
标题翻译：存储单元制造方法
公开(公告)号：US20050032311A1
公开(公告)日：2005-02-10
申请号：US10899436
申请日：2004-07-26
申请人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
发明人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.
摘要翻译：制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造栅电极的电连接。

80. 发明授权

US06750095B1 Integrated circuit with vertical transistors 失效
标题翻译：集成电路与垂直晶体管
公开(公告)号：US06750095B1
公开(公告)日：2004-06-15
申请号：US09787966
申请日：2001-05-29
申请人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
发明人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/1052 , H01L27/10823 , H01L27/112 , H01L27/11273
摘要： A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.
摘要翻译：制造具有垂直MOS晶体管的集成电路的方法包括：掺杂衬底以形成与其表面相邻的层，并形成用作晶体管的第一源极/漏极区的下掺杂层。晶体管的沟道区域通过在下层上掺杂中心层而形成。通过在中心层上方掺杂上层形成第二源/漏区。上层，中层和下层形成具有相对的第一和第二面的层序列。在第一面上形成连接结构，以电连接沟道区和衬底。连接结构至少横向邻接中心层和下层，并延伸到基底中。在第二面上形成栅电介质和相邻栅电极。

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