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1. 发明申请

US20050032311A1 Fabrication method for memory cell 失效
标题翻译：存储单元制造方法
公开(公告)号：US20050032311A1
公开(公告)日：2005-02-10
申请号：US10899436
申请日：2004-07-26
申请人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
发明人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.
摘要翻译：制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造栅电极的电连接。

2. 发明授权

US06982202B2 Fabrication method for memory cell 失效
标题翻译：存储单元制造方法
公开(公告)号：US06982202B2
公开(公告)日：2006-01-03
申请号：US10899436
申请日：2004-07-26
申请人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
发明人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.
摘要翻译：制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造栅电极的电连接。

3. 发明申请

US20070057301A1 Method of manufacturing a transistor, a method of manufacturing a memory device and transistor 失效
标题翻译：制造晶体管的方法，制造存储器件和晶体管的方法
公开(公告)号：US20070057301A1
公开(公告)日：2007-03-15
申请号：US11222540
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L29/94
CPC分类号： H01L29/66621 , H01L21/28114 , H01L27/10876 , H01L27/10894 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.
摘要翻译：公开了制造晶体管的方法。该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间口袋栅极绝缘材料设置在有源区域和凹槽之间的界面处以及有源区域和凹穴之间的界面处。沉积栅电极材料以填充凹槽和两个凹穴。

4. 发明申请

US20060110884A1 Method of manufacturing a transistor and a method of forming a memory device 失效
标题翻译：制造晶体管的方法和形成存储器件的方法
公开(公告)号：US20060110884A1
公开(公告)日：2006-05-25
申请号：US11222613
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L27/10823 , G11C11/404 , H01L21/76897 , H01L27/0207 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the isolation trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between the two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.
摘要翻译：一种制造晶体管的方法。在一个实施例中，该方法包括通过在衬底中限定栅极沟槽来形成栅电极。在每个隔离沟槽中的与槽相邻的位置处限定板状部分，使得两个板状部分将与沟槽连接，并且沟槽设置在两个板状部分之间。在一个实施例中，通过蚀刻工艺限定两个板状部分，该蚀刻工艺相对于半导体衬底材料选择性地蚀刻隔离沟槽的隔离材料。栅极绝缘材料设置在有源区域和沟槽之间的界面处，并且在有源区域和板状部分之间的界面处设置，并且沉积栅电极材料以填充沟槽和两个板状部分。

5. 发明授权

US07763513B2 Integrated circuit device and method of manufacture 失效
标题翻译：集成电路器件及其制造方法
公开(公告)号：US07763513B2
公开(公告)日：2010-07-27
申请号：US11222540
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28114 , H01L27/10876 , H01L27/10894 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.
摘要翻译：公开了制造晶体管的方法。该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间口袋栅极绝缘材料设置在有源区域和凹槽之间的界面处以及在有源区域和凹穴之间的界面处。沉积栅电极材料以填充凹槽和两个凹穴。

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