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US06750095B1 Integrated circuit with vertical transistors 失效
标题翻译：集成电路与垂直晶体管
公开(公告)号：US06750095B1
公开(公告)日：2004-06-15
申请号：US09787966
申请日：2001-05-29
申请人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
发明人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/1052 , H01L27/10823 , H01L27/112 , H01L27/11273
摘要： A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.
摘要翻译：制造具有垂直MOS晶体管的集成电路的方法包括：掺杂衬底以形成与其表面相邻的层，并形成用作晶体管的第一源极/漏极区的下掺杂层。晶体管的沟道区域通过在下层上掺杂中心层而形成。通过在中心层上方掺杂上层形成第二源/漏区。上层，中层和下层形成具有相对的第一和第二面的层序列。在第一面上形成连接结构，以电连接沟道区和衬底。连接结构至少横向邻接中心层和下层，并延伸到基底中。在第二面上形成栅电介质和相邻栅电极。

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