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1. 发明申请

US20060022248A1 Electronic data memory device for a high read current 审中-公开
标题翻译：用于高读取电流的电子数据存储器件
公开(公告)号：US20060022248A1
公开(公告)日：2006-02-02
申请号：US11167386
申请日：2005-06-27
申请人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
发明人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10873 , H01L29/7851
摘要： Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).
摘要翻译：用于高读取电流的电子数据存储器件本发明提供一种布置在衬底（401）上并具有至少一个存储单元（100）的存储器件。存储单元包括用于存储电荷的存储电容器（200）晶体管（300），用于选择存储单元（100）。选择晶体管包括第一导电电极（301），第二导电电极（302）和控制电极（303），控制电极（303）由栅极单元（400）提供，栅极单元（400）具有从基板（401），其被栅极氧化物层（406）和栅极电极层（403）包围，使得第一和第二栅极元件（408a，408b）设置在第一和第二栅极元件（408a，408b）的相对侧向区域所述翅片（405），第三栅极元件（408c）设置在所述鳍状物（405）的与所述基板（401）的表面平行的区域。

2. 发明授权

US06995418B2 Integrated semiconductor storage with at least a storage cell and procedure 失效
公开(公告)号：US06995418B2
公开(公告)日：2006-02-07
申请号：US10840328
申请日：2004-05-07
申请人： Andreas Spitzer
发明人： Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L21/84 , H01L27/10829 , H01L27/10832 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/11 , H01L27/1203 , H01L29/0895 , H01L29/42364 , H01L29/66181
摘要： The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.

3. 发明申请

US20060192271A1 Method of manufacturing a dielectric layer and corresponding semiconductor device 失效
公开(公告)号：US20060192271A1
公开(公告)日：2006-08-31
申请号：US11067496
申请日：2005-02-28
申请人： Andreas Spitzer , Elke Erben
发明人： Andreas Spitzer , Elke Erben
IPC分类号： H01L23/58 , H01L21/469
CPC分类号： H01L21/02112 , C23C16/40 , H01G4/085 , H01G4/1209 , H01L21/02123 , H01L21/02145 , H01L21/02271 , H01L21/0228 , H01L21/3141 , H01L21/31645 , H01L28/40 , H01L28/56 , H01L28/90
摘要： A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.

4. 发明申请

US20070278549A1 Integrated Circuit with a Transistor Structure Element 审中-公开
标题翻译：具有晶体管结构元件的集成电路
公开(公告)号：US20070278549A1
公开(公告)日：2007-12-06
申请号：US11775719
申请日：2007-07-10
申请人： Andreas Spitzer
发明人： Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L21/84 , H01L27/10829 , H01L27/10832 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/11 , H01L27/1203 , H01L29/0895 , H01L29/42364 , H01L29/66181
摘要： An integrated semiconductor memory includes at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region, and a region arranged between the first and the second source/drain region. The structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric is arranged on the structure element, and a word line is arranged on the gate dielectric.
摘要翻译：集成半导体存储器包括至少一个具有至少一个晶体管的存储单元，该晶体管在接通状态下形成反向通道。晶体管包括具有第一源极/漏极区域，第二源极/漏极区域和布置在第一和第二源极/漏极区域之间的区域的结构元件。结构元件通过绝缘层与半导体衬底绝缘，栅极电介质布置在结构元件上，并且字线被布置在栅极电介质上。

5. 发明申请

US20060071261A1 Integrated semiconductor storage with at least a storage cell and procedure 有权
标题翻译：具有至少一个存储单元和程序的集成半导体存储器
公开(公告)号：US20060071261A1
公开(公告)日：2006-04-06
申请号：US11283804
申请日：2005-11-22
申请人： Andreas Spitzer
发明人： Andreas Spitzer
IPC分类号： H01L29/94
CPC分类号： H01L27/10861 , H01L21/84 , H01L27/10829 , H01L27/10832 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/11 , H01L27/1203 , H01L29/0895 , H01L29/42364 , H01L29/66181
摘要： The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.
摘要翻译：本发明涉及具有至少一个存储单元的集成半导体存储器，该至少一个存储单元具有至少一个在开启状态下形成反向通道的晶体管。晶体管包括具有第一源极/漏极区域，第二源极/漏极区域和布置在第一和第二源极/漏极区域之间的区域的结构元件，该结构元件通过绝缘层与半导体衬底绝缘，栅极电介质被布置在结构元件上，字线被布置在栅极电介质上。

6. 发明申请

US20050041495A1 Integrated semiconductor storage with at least a storage cell and procedure 失效
标题翻译：具有至少一个存储单元和程序的集成半导体存储器
公开(公告)号：US20050041495A1
公开(公告)日：2005-02-24
申请号：US10840328
申请日：2004-05-07
申请人： Andreas Spitzer
发明人： Andreas Spitzer
IPC分类号： H01L21/334 , H01L21/8242 , H01L21/8244 , H01L21/84 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/08 , H01L29/423 , G11C7/00
CPC分类号： H01L27/10861 , H01L21/84 , H01L27/10829 , H01L27/10832 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/11 , H01L27/1203 , H01L29/0895 , H01L29/42364 , H01L29/66181
摘要： The invention relates to an integrated semiconductor memory (10) with at least one memory cell (1) having at least one transistor (3) which forms an inversion channel (34) in the switched-on state, the transistor (3) having a structure element (4) having a first source/drain region (5), a second source/drain region (6) and a region (4b) arranged between the first (5) and the second source/drain region (6), the structure element (4) being insulated from a semiconductor substrate (20) by an insulation layer (11), a gate dielectric (9) being arranged on the structure element (4) and a word line (16) being arranged on the gate dielectric (9), the gate dielelctric (9) being a high-resistance tunnel contact having a first region (31), the layer thickness (d) of which is so small that, in the switched-off state of the transistor (3), majority charge carriers generated thermally in the structure element (4) pass into the word line (16) by direct tunneling through the gate dielectric (9), and the entire region (4b) of the structure element (4) which region is arranged between the first (5) and the second source/drain region (6) being depleted of majority charge carriers in the switched-on state of the transistor (3). By virtue of the first region of the gate dielectric (9), majority charge carriers are conducted away from the structure element (4) into the word line in the off state of the transistor and parasitic effects which could arise on account of accumulating majority charge carriers are avoided.
摘要翻译：本发明涉及具有至少一个存储单元（1）的集成半导体存储器（10），所述至少一个存储单元（1）具有至少一个晶体管（3），所述晶体管在所述导通状态下形成反转通道（34），所述晶体管（3）具有具有第一源极/漏极区域（5），第二源极/漏极区域（6）和布置在第一源极/漏极区域（6）之间的区域（4b）的结构元件（4）结构元件（4）通过绝缘层（11）与半导体衬底（20）绝缘，栅极电介质（9）布置在结构元件（4）上，并且字线（16）布置在栅极电介质（9）中，所述栅极导体（9）是具有第一区域（31）的高电阻隧道触点，所述第一区域（31）的层厚度（d）小到在晶体管（3）的截止状态下，，在结构元件（4）中热产生的多数电荷载流子通过直接穿过栅极电介质（9）穿过字线（16），并且t 在晶体管（3）的接通状态下，布置在第一（5）和第二源极/漏极区域（6）之间的结构元件（4）的整个区域（4b）被耗尽多数电荷载流子）。由于门电介质（9）的第一区域，在晶体管的截止状态下，多数电荷载流子从结构元件（4）导入字线，并且由于累积多数电荷而可能产生寄生效应承运人被避免。

7. 发明申请

US20130264654A1 Integrated Switching Device with Parallel Rectifier Element 审中-公开
标题翻译：具有并联整流元件的集成开关器件
公开(公告)号：US20130264654A1
公开(公告)日：2013-10-10
申请号：US13441038
申请日：2012-04-06
申请人： Rolf Weis , Andreas Spitzer
发明人： Rolf Weis , Andreas Spitzer
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L23/481 , H01L25/074 , H01L25/18 , H01L27/0688 , H01L29/4236 , H01L29/78 , H01L29/7835 , H01L2924/0002 , H03K17/102 , H01L2924/00
摘要： An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer.
摘要翻译：集成电路包括具有第一半导体层的半导体本体和在半导体本体的垂直方向上与第一半导体层相邻布置的第二半导体层。集成电路还包括具有控制端子和第一负载端子和第二负载端子之间的负载路径的开关装置，以及与负载路径的至少一个部分并联连接的整流元件。开关器件集成在第一半导体层中，并且整流元件集成在第二半导体层中。

8. 发明授权

US07241657B2 Integrated semiconductor storage with at least a storage cell and procedure 有权
标题翻译：具有至少一个存储单元和程序的集成半导体存储器
公开(公告)号：US07241657B2
公开(公告)日：2007-07-10
申请号：US11283804
申请日：2005-11-22
申请人： Andreas Spitzer
发明人： Andreas Spitzer
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/84 , H01L27/10829 , H01L27/10832 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/11 , H01L27/1203 , H01L29/0895 , H01L29/42364 , H01L29/66181
摘要： The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.
摘要翻译：本发明涉及具有至少一个存储单元的集成半导体存储器，该至少一个存储单元具有至少一个在开启状态下形成反向通道的晶体管。晶体管包括具有第一源极/漏极区域，第二源极/漏极区域和布置在第一和第二源极/漏极区域之间的区域的结构元件，该结构元件通过绝缘层与半导体衬底绝缘，栅极电介质被布置在结构元件上，字线被布置在栅极电介质上。

9. 发明授权

US6165835A Method for producing a silicon capacitor 失效
标题翻译：硅电容器的制造方法
公开(公告)号：US6165835A
公开(公告)日：2000-12-26
申请号：US341937
申请日：1999-07-20
申请人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
发明人： Hermann Wendt , Hans Reisinger , Andreas Spitzer , Reinhard Stengl , Ulrike Gruning , Josef Willer , Wolfgang Honlein , Volker Lehmann
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10861 , H01L29/66181 , Y10S438/96
摘要： In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.
摘要翻译： PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质层（4）和导电层（5），而不填充孔结构（2）。为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面压缩机械应力。

10. 发明授权

US07531405B2 Method of manufacturing a dielectric layer and corresponding semiconductor device 失效
标题翻译：制造电介质层的方法和相应的半导体器件
公开(公告)号：US07531405B2
公开(公告)日：2009-05-12
申请号：US11067496
申请日：2005-02-28
申请人： Andreas Spitzer , Elke Erben
发明人： Andreas Spitzer , Elke Erben
IPC分类号： H01L21/338 , H01L21/8238 , H01L21/8244 , H01L21/8242 , H01L21/8234 , H01L21/336 , H01L21/8222 , H01L21/20 , H01L21/473
CPC分类号： H01L21/02112 , C23C16/40 , H01G4/085 , H01G4/1209 , H01L21/02123 , H01L21/02145 , H01L21/02271 , H01L21/0228 , H01L21/3141 , H01L21/31645 , H01L28/40 , H01L28/56 , H01L28/90
摘要： A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.
摘要翻译：形成多晶介电层，其中电介质层包括含有氧化物或氮化物的第一介电材料和有助于电介质层重量小于1重量％的第二材料，形成焓不足的非导电氧化物或氮化物第一介电材料的焓使得沿着第一介电材料的晶界的漏电流减小。

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