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61. 发明授权

US09425122B2 Electronic component package and method for manufacturing the same 有权
标题翻译：电子元件封装及其制造方法
公开(公告)号：US09425122B2
公开(公告)日：2016-08-23
申请号：US14422505
申请日：2013-12-20
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Koji Kawakita , Seiichi Nakatani , Susumu Sawada , Yoshihisa Yamashita
IPC分类号： H01L33/00 , H01L23/367 , H01L33/62 , H01L33/64 , H01L33/52 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/538 , H01L33/50 , H01L23/36 , H01L25/075 , H01L23/495
CPC分类号： H01L23/367 , H01L21/4846 , H01L21/4871 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/3135 , H01L23/36 , H01L23/49575 , H01L23/5389 , H01L24/97 , H01L25/0753 , H01L33/507 , H01L33/52 , H01L33/62 , H01L33/64 , H01L2224/16 , H01L2224/16225 , H01L2224/16245 , H01L2224/48091 , H01L2224/73265 , H01L2924/12041 , H01L2924/12042 , H01L2924/181 , H01L2924/19105 , H01L2933/0041 , H01L2933/005 , H01L2933/0066 , H01L2933/0075 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for manufacturing an electronic component packages is provided, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. A combination of a formation process of a plurality of metal plating layers and a patterning process of the plurality of metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, and the patterning process being performed by a patterning of at least two of the plurality of metal plating layers.
摘要翻译：提供了一种电子部件封装的制造方法，其中提供封装前体，其中将电子部件嵌入到密封树脂层中，使得电子部件的电极在密封树脂层的表面露出。提供多个金属镀层的形成过程和多个金属镀层的图案化工艺的组合以形成阶梯状金属镀层，形成工艺通过相继的干式和湿式电镀工艺进行，并且通过图案化多个金属镀层中的至少两个来执行图案化工艺。

62. 发明申请

US20160240949A1 LOW PROFILE ZERO/LOW INSERTION FORCE PACKAGE TOP SIDE FLEX CABLE CONNECTOR ARCHITECTURE 审中-公开
标题翻译：低配置零/低插入力封装顶部边缘电缆连接器架构
公开(公告)号：US20160240949A1
公开(公告)日：2016-08-18
申请号：US15135413
申请日：2016-04-21
申请人： Sanka Ganesan , Ram S. Viswanath
发明人： Sanka Ganesan , Ram S. Viswanath
IPC分类号： H01R12/79 , H05K1/14 , H01L23/367 , H01L23/498 , H01L23/00
CPC分类号： H01R12/79 , H01B7/04 , H01L23/3675 , H01L23/49811 , H01L23/49838 , H01L24/17 , H01L24/72 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01R12/62 , H05K1/142 , H05K1/147 , H05K3/361 , H05K2201/10318 , H05K2201/10325 , H05K2201/10424 , H05K2201/10674 , H05K2201/10681 , H05K2201/2009 , H01L2224/0401
摘要： An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
摘要翻译：介绍了一种集成电路封装。在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

63. 发明授权

US09414500B2 Compliant printed flexible circuit 有权
标题翻译：符合印刷柔性电路
公开(公告)号：US09414500B2
公开(公告)日：2016-08-09
申请号：US13320285
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K3/12 , H01L23/498 , H05K1/11 , H05K3/40 , H05K3/46 , H05K1/02 , H05K1/16 , H05K3/10 , H05K3/20 , H05K3/24 , H05K3/28
CPC分类号： H05K1/181 , H01L23/4985 , H01L2224/16 , H01L2924/09701 , H01L2924/12044 , H01L2924/3011 , H05K1/0216 , H05K1/0221 , H05K1/0256 , H05K1/0274 , H05K1/0284 , H05K1/118 , H05K1/16 , H05K3/107 , H05K3/1258 , H05K3/207 , H05K3/246 , H05K3/28 , H05K3/4007 , H05K3/4664 , H05K3/4694 , H05K2201/0344 , H05K2201/0367 , H05K2201/09109 , H05K2201/10674 , H05K2201/10734 , Y10T29/49155
摘要： A compliant printed flexible circuit including a flexible polymeric film and at least one dielectric layer bonded to the polymeric film with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to form a circuit geometry. At least one dielectric covering layer is printed over at least the circuit geometry. Openings can be printed in the dielectric covering layer to provide access to at least a portion of the circuit geometry.
摘要翻译：包括柔性聚合物膜和柔性聚合物膜的柔性印刷柔性电路以及与聚合物膜结合的至少一个介电层，其具有对应于目标电路几何形状的凹部。在至少一部分凹部中印刷导电材料以形成电路几何形状。至少一个电介质覆盖层至少印刷在电路几何形状上。开口可以印刷在电介质覆盖层中以提供对电路几何形状的至少一部分的访问。

64. 发明授权

US09404942B2 Coaxial probe structure of elongated electrical conductors projecting from a support structure 有权
标题翻译：从支撑结构突出的细长电导体的同轴探针结构
公开(公告)号：US09404942B2
公开(公告)日：2016-08-02
申请号：US14175116
申请日：2014-02-07
申请人： GLOBALFOUNDRIES INC.
发明人： Brian Samuel Beaman , Keith Edward Fogel , Paul Alfred Lauro , Yun-Hsin Liao , Daniel Peter Morris , Da-Yuan Shih
IPC分类号： G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L23/498 , H01L23/538 , H01L25/065
CPC分类号： G01R1/07307 , G01R1/06711 , G01R1/0675 , G01R1/06772 , G01R1/07342 , G01R1/07371 , G01R1/07378 , G01R3/00 , G01R31/2886 , H01L23/49827 , H01L23/5384 , H01L25/0652 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/78301 , H01L2924/00013 , H01L2924/00014 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/1627 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： Coaxial probe structures include a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
摘要翻译：同轴探头结构包括从支撑表面突出的多个分立的绝缘细长电导体，其可用作用于测试电子装置（例如集成电路装置和其他电子部件）的电互连的探针，特别是用于具有刚性的集成电路装置的测试互连焊盘和具有高密度互连焊盘的多芯片模块封装。通过提供高密度同轴探针的方法制造同轴探针结构。

65. 发明申请

US20160218133A1 PHOTOSENSITIVE MODULE AND METHOD FOR FORMING THE SAME 有权
标题翻译：感光性模块及其形成方法
公开(公告)号：US20160218133A1
公开(公告)日：2016-07-28
申请号：US15006052
申请日：2016-01-25
申请人： XINTEC INC.
发明人： Yen-Shih HO , Tsang-Yu LIU , Chi-Chang LIAO
IPC分类号： H01L27/146
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14683 , H01L2224/16
摘要： A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.
摘要翻译：提供一种形成光敏模块的方法。该方法包括提供感测装置。感测装置包括位于基板上的导电垫。第一开口穿透衬底并暴露导电垫。再分布层位于第一开口中，以电连接到导电垫。盖板位于基板上并覆盖导电垫。该方法还包括移除感测装置的盖板。该方法还包括在移除盖板之后将感测装置接合到电路板。第一开口中的再分配层被暴露并面向电路板。此外，该方法包括将对应于感测装置的光学部件安装在电路板上。还提供了通过该方法形成的感光模块。

66. 发明授权

US09401379B2 Image sensor module and method for producing such a module 有权
标题翻译：图像传感器模块及其制造方法
公开(公告)号：US09401379B2
公开(公告)日：2016-07-26
申请号：US14004632
申请日：2012-01-16
申请人： Hartmut Rohde , Ulrich Seger , Thomas Kurzweil , Uwe Apel , Marc Zimmermann , Anja Beckerle , Klaus Zeh , Gerald Brinks
发明人： Hartmut Rohde , Ulrich Seger , Thomas Kurzweil , Uwe Apel , Marc Zimmermann , Anja Beckerle , Klaus Zeh , Gerald Brinks
IPC分类号： H01L27/00 , H01L27/146 , H04N5/225 , B60R11/04 , B60R11/00
CPC分类号： H01L27/14618 , B60R11/04 , B60R2011/0026 , H01L27/14683 , H01L2224/16 , H04N5/2251 , H04N5/2257
摘要： An image sensor module includes an image sensor bearer and an image sensor, the image sensor bearer being fashioned as an injection-molded circuit bearer, and the image sensor being situated on the image sensor bearer, and the image sensor bearer including at least one holding device that is integrally formed on the image sensor bearer.
摘要翻译：图像传感器模块包括图像传感器承载件和图像传感器，所述图像传感器承载件被形成为注射成型的电路承载件，并且所述图像传感器位于所述图像传感器承载件上，并且所述图像传感器承载件包括至少一个保持件整体形成在图像传感器承载体上的装置。

67. 发明授权

US09397021B2 Electrical connector 有权
标题翻译：电连接器
公开(公告)号：US09397021B2
公开(公告)日：2016-07-19
申请号：US14538352
申请日：2014-11-11
申请人： LOTES CO., LTD
发明人： Ted Ju
IPC分类号： H01L23/32 , H01L23/498 , H01L23/00
CPC分类号： H01L23/32 , H01L23/49811 , H01L23/49827 , H01L23/49866 , H01L24/13 , H01L24/72 , H01L24/73 , H01L24/81 , H01L24/90 , H01L24/91 , H01L2224/13076 , H01L2224/13111 , H01L2224/13205 , H01L2224/13209 , H01L2224/13339 , H01L2224/13347 , H01L2224/1339 , H01L2224/13409 , H01L2224/13411 , H01L2224/13418 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/73251 , H01L2224/8114 , H01L2224/81191 , H01L2224/81192 , H01L2224/81405 , H01L2224/81409 , H01L2224/81505 , H01L2224/81509 , H01L2224/81639 , H01L2224/81647 , H01L2224/8169 , H01L2224/81709 , H01L2224/81711 , H01L2224/81718 , H01L2224/81901 , H01L2924/3841 , H01L2924/00014 , H01L2924/014 , H01L2924/0105 , H01L2924/01031 , H01L2924/013 , H01L2924/01049 , H01L2224/72 , H01L2224/16
摘要： An electrical connector for electrically connecting a chip module to a circuit board, includes an insulating body, multiple conducting bodies, and multiple pieces of low melting point metal. The insulating body has multiple accommodating spaces. Each accommodating space runs through upper and lower surfaces of the insulating body. The multiple conducting bodies are respectively received in the accommodating spaces. Two ends of each conducting body are exposed on the upper and lower surfaces of the insulating body. The low melting point metal is gallium or gallium alloy. Each piece of the low melting point metal is correspondingly arranged at at least one end of one of the conducting bodies. The low melting point metal protrudes from the insulating body, and is electrically connected to the chip module.
摘要翻译：用于将芯片模块电连接到电路板的电连接器包括绝缘体，多个导电体和多片低熔点金属。绝缘体具有多个容纳空间。每个容纳空间穿过绝缘体的上表面和下表面。多个导电体分别容纳在容纳空间中。每个导电体的两端暴露在绝缘体的上表面和下表面上。低熔点金属是镓或镓合金。每片低熔点金属相应地布置在一个导电体的至少一端。低熔点金属从绝缘体突出并与芯片模块电连接。

68. 发明申请

US20160197244A1 METHOD OF ATTACHING A LIGHT EMITTING DEVICE TO A SUPPORT SUBSTRATE 有权
标题翻译：将发光装置连接到支撑基板的方法
公开(公告)号：US20160197244A1
公开(公告)日：2016-07-07
申请号：US15066237
申请日：2016-03-10
申请人： KONINKLIJKE PHILIPS N.V.
发明人： DANIEL ALEXANDER STEIGERWALD , JEROME CHANDRA BHAT , SALMAN AKRAM
IPC分类号： H01L33/48 , H01L33/62 , H01L33/58 , H01L33/46
CPC分类号： H01L33/483 , H01L25/075 , H01L25/50 , H01L33/0079 , H01L33/46 , H01L33/50 , H01L33/58 , H01L33/62 , H01L2224/16 , H01L2933/0066
摘要： A method according to embodiments of the invention includes providing a wafer of semiconductor light emitting devices, each semiconductor light emitting device including a light emitting layer sandwiched between an n-type region and a p-type region. A wafer of support substrates is provided, each support substrate including a body. The wafer of semiconductor light emitting devices is bonded to the wafer of support substrates. Vias are formed extending through the entire thickness of the body of each support substrate.
摘要翻译：根据本发明实施例的方法包括提供半导体发光器件的晶片，每个半导体发光器件包括夹在n型区域和p型区域之间的发光层。提供了一组支撑基板，每个支撑基板包括主体。半导体发光器件的晶片被结合到支撑衬底的晶片上。形成延伸穿过每个支撑基板的主体的整个厚度的通孔。

69. 发明授权

US09386695B2 Wiring substrate having multiple core substrates 有权
标题翻译：具有多个芯基板的布线基板
公开(公告)号：US09386695B2
公开(公告)日：2016-07-05
申请号：US13855762
申请日：2013-04-03
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Jun Furuichi , Akihiko Tateiwa , Naoyuki Koizumi
IPC分类号： H05K1/09 , H05K1/11 , H05K1/02 , H05K3/46 , H05K3/00 , H01L23/14 , H01L23/15 , H01L23/498
CPC分类号： H05K1/115 , H01L23/145 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L2224/16 , H05K1/0298 , H05K3/002 , H05K3/4605 , H05K3/4694 , H05K2201/09227
摘要： There is provided a wiring substrate including: a core substrate including: a first core substrate including: a plate-shaped first glass substrate; and a first through electrode formed through the first glass substrate; a second core substrate including: a plate-shaped second glass substrate; and a second through electrode formed through the second glass substrate, wherein a diameter of the second through electrode is different from that of the first through electrode; and an insulating member encapsulating the first and second core substrates, and a wiring layer formed on at least one surface of the core substrate. The first and second core substrates are arranged to be separated from each other when viewed from a top.
摘要翻译：提供一种布线基板，包括：芯基板，包括：第一芯基板，包括：板状第一玻璃基板; 以及通过所述第一玻璃基板形成的第一贯通电极; 第二芯基板，包括：板状第二玻璃基板; 以及通过所述第二玻璃基板形成的第二贯通电极，其中所述第二贯通电极的直径与所述第一贯通电极的直径不同; 以及封装所述第一和第二芯基板的绝缘构件，以及形成在所述芯基板的至少一个表面上的布线层。第一和第二芯基板被布置成当从顶部观察时彼此分离。

70. 发明授权

US09385014B2 Flip-chip package covered with tape 有权
公开(公告)号：US09385014B2
公开(公告)日：2016-07-05
申请号：US12962479
申请日：2010-12-07
申请人： Naomi Masuda
发明人： Naomi Masuda
IPC分类号： H01L21/67 , H01L21/56 , H01L23/00
CPC分类号： H01L21/67126 , H01L21/565 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/16 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/75 , H01L2224/75743 , H01L2224/83191 , H01L2224/83192 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/16152 , H01L2924/3511 , Y10T156/1798 , H01L2924/00 , H01L2924/00012
摘要： A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.

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