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1. 发明申请

US20190037703A1 Method and Plater Arrangement for Failure-Free Copper Filling of a Hole in a Component Carrier 审中-公开
公开(公告)号：US20190037703A1
公开(公告)日：2019-01-31
申请号：US16049512
申请日：2018-07-30
申请人： AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
发明人： Ares Wang , Yee-Bing Ling , Annie Tay
IPC分类号： H05K3/00 , H05K3/46 , H05K3/24 , H05K1/02
CPC分类号： H05K3/0094 , H05K1/0298 , H05K3/0026 , H05K3/0055 , H05K3/241 , H05K3/244 , H05K3/423 , H05K3/4644 , H05K2201/0344 , H05K2201/09563 , H05K2203/1476 , Y10T29/49165
摘要： A method of filling a hole formed in a component carrier with copper is disclosed. The method comprises i) forming a layer of an electrically conductive material covering at least part of a surface of a wall, wherein the wall delimits the hole, and subsequently ii) covering at least partially the layer and filling at least partially an unfilled volume of the hole with copper using a plating process including a bath. Hereby, the bath comprises a concentration of a copper ion, in particular Cu2+, in a range between 50 g/L and 75 g/L, in particular in a range between 60 g/L and 70 g/L.

2. 发明授权

US09699906B2 Hybrid printed circuit assembly with low density main core and embedded high density circuit regions 有权
公开(公告)号：US09699906B2
公开(公告)日：2017-07-04
申请号：US14408205
申请日：2013-03-13
申请人： HSIO TECHNOLOGIES, LLC
发明人： James Rathburn
IPC分类号： H05K3/02 , H05K3/10 , H05K1/18 , H05K3/46 , H05K1/02 , H05K1/16
CPC分类号： H05K1/181 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H05K1/0216 , H05K1/0256 , H05K1/0284 , H05K1/16 , H05K3/107 , H05K3/4664 , H05K3/4694 , H05K2201/0344 , H05K2201/10674 , H05K2201/10734 , Y10T29/49155 , H01L2924/00014
摘要： A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

3. 发明申请

US20140339699A1 UNDER BALL METALLURGY (UBM) FOR IMPROVED ELECTROMIGRATION 有权
标题翻译：用于改进电化学的金属（UBM）
公开(公告)号：US20140339699A1
公开(公告)日：2014-11-20
申请号：US14447908
申请日：2014-07-31
申请人： International Business Machines Corporation
发明人： Charles L. Arvin , Minhua Lu , Eric D. Perfecto , David J. Russell , Wolfgang Sauter , Krystyna W. Semkow , Thomas A. Wassick
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/49816 , H01L21/76843 , H01L21/76885 , H01L23/49866 , H01L2224/11 , H05K1/09 , H05K3/3478 , H05K3/4007 , H05K2201/0338 , H05K2201/0341 , H05K2201/0344 , H05K2201/09745 , H05K2203/041
摘要： An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.
摘要翻译：一种互连结构，其包括其中存在电气部件的基板以及与接触焊盘接触的凸起下冶金（UBM）堆叠，所述凸块冶金（UBM）堆叠存在于所述基板中的所述电气部件。 UBM堆叠包括与接触焊盘直接接触电气部件的金属粘合层，与金属粘附层层直接接触的铜（Cu）种子层，第一镍（Ni）阻挡层，存在于铜（Cu）种子层的直接接触中，以及存在于第一镍（Ni）阻挡层上的至少一个铜（Cu）导体层和至少一个第二镍（Ni）阻挡层的层状结构。第二镍（Ni）阻挡层上可能存在焊球。

4. 发明申请

US20140076618A1 METHOD OF FORMING GOLD THIN FILM AND PRINTED CIRCUIT BOARD 审中-公开
标题翻译：形成金薄膜和印刷电路板的方法
公开(公告)号：US20140076618A1
公开(公告)日：2014-03-20
申请号：US13692643
申请日：2012-12-03
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD. , RESEARCH & BUSINESS FOUNDATION SUNGK
发明人： Seong Min CHO , Chan Hwa CHUNG , Chang Yong AN , Chang Sup RYU , Hyo Seung NAM
IPC分类号： H05K3/18 , H05K1/09
CPC分类号： H05K3/188 , C23C18/1637 , C23C18/1651 , C23C18/1844 , C23C18/36 , C23C18/44 , C23C18/48 , C23C18/54 , H05K1/09 , H05K3/244 , H05K2201/0344 , H05K2203/073
摘要： There is provided a method of forming a gold thin film, the method including: forming a nickel plating layer on a surface of an object through electroless nickel (Ni) plating; forming a palladium-copper mixture plating layer on the nickel plating layer through electroless plating using a palladium-copper (Pd—Cu) mixture; and forming a first gold thin film by immersing the palladium-copper mixture plating layer in a gold (Au) galvanic electrolytic liquid to replace a portion of copper (Cu) particles in the palladium-copper mixture plating layer with gold particles through a replacement reaction.
摘要翻译：提供一种形成金薄膜的方法，所述方法包括：通过无电镀镍（Ni）电镀在物体的表面上形成镀镍层; 通过使用钯 - 铜（Pd-Cu）混合物的化学镀来在镍镀层上形成钯 - 铜混合物镀层; 并且通过将钯 - 铜混合物镀层浸入金（Au）电解电解液中形成第一金薄膜，以通过置换反应用金颗粒代替钯 - 铜混合物镀层中的一部分铜（Cu）颗粒。

5. 发明申请

US20120088120A1 METAL-CLAD LAMINATE AND METHOD FOR PRODUCTION OF METAL-CLAD LAMINATE 审中-公开
标题翻译：金属层压板及金属层压板的生产方法
公开(公告)号：US20120088120A1
公开(公告)日：2012-04-12
申请号：US13375918
申请日：2010-06-02
申请人： Kimiko Fujisawa , Kenichi Ohga
发明人： Kimiko Fujisawa , Kenichi Ohga
IPC分类号： B32B15/08 , B05D1/36 , C23C28/02 , C25D5/56
CPC分类号： B32B15/08 , B32B2307/3065 , B32B2457/00 , C23C18/1641 , C23C18/1653 , C23C18/2073 , C23C18/40 , H05K1/0393 , H05K3/181 , H05K2201/0129 , H05K2201/0344 , Y10T428/12569
摘要： Disclosed is a metal-clad laminate and a method for producing a metal-clad laminate wherein adhesion between a metal layer and a thermoplastic film serving as a base material is improved, the deposition rate of a plating coat on the base material is improved, and the insulating resistance after etching is properly adjusted at the same time.The metal-clad laminate comprises a base material that is composed of a thermoplastic polymer film, a base metal layer that is provided on the surface of the base material, and an upper metal layer that is provided on the surface of the base metal layer.The base metal layer is made of a copper alloy that contains 0.05-0.21 mass % of phosphorus, and the upper metal layer is made of copper or a copper alloy.
摘要翻译：公开了一种覆金属箔层压板及其制造方法，其中金属层和用作基材的热塑性膜之间的粘附性得到改善，镀层在基材上的沉积速率提高，蚀刻后的绝缘电阻同时适当调整。覆金属层压板包括由热塑性聚合物膜，设置在基材的表面上的基底金属层和设置在基底金属层的表面上的上部金属层构成的基材。基底金属层由含有0.05-0.21质量％的磷的铜合金制成，上部金属层由铜或铜合金构成。

6. 发明授权

US08147904B2 Metal clad laminate and method for manufacturing metal clad laminate 有权
标题翻译：金属复合层压板及其制造方法
公开(公告)号：US08147904B2
公开(公告)日：2012-04-03
申请号：US12556143
申请日：2009-09-09
申请人： Satoru Zama , Kenichi Ohga
发明人： Satoru Zama , Kenichi Ohga
IPC分类号： B32B3/10
CPC分类号： H05K3/022 , C22C1/002 , C23C18/31 , C25D5/50 , H05K1/0393 , H05K3/181 , H05K3/38 , H05K2201/0129 , H05K2201/0344 , H05K2203/1105 , Y10T428/24322 , Y10T428/31678
摘要： A method for manufacturing a metal clad laminate having a film and a metal layer formed of a foundation layer and an upper layer includes the steps of forming the foundation layer on at least a part of a surface of the film by plating to obtain a first laminate; forming the upper layer on the first laminate by plating to obtain a second laminate; and heating the second laminate to obtain the metal clad laminate. Further, the film is a flexible thermoplastic polymer film, the foundation layer is formed of a nickel alloy, the upper layer is formed of copper, at least one of the foundation layer and the upper layer has a compression stress before the step of heating the second laminate, and the metal clad laminate shrinks in a planar direction of the film during the step of heating the second laminate.
摘要翻译：一种具有由基底层和上层形成的膜和金属层的金属覆层叠层的制造方法，包括以下步骤：通过电镀在所述膜的至少一部分表面上形成所述基底层，以获得第一层压体 ; 通过电镀在第一层压体上形成上层以获得第二层压体; 并加热第二层压板以获得覆金属层压板。此外，该膜是柔性热塑性聚合物膜，基底层由镍合金形成，上层由铜形成，基础层和上层中的至少一个在加热步骤之前具有压缩应力第二层压体，并且在加热第二层压体的步骤期间，金属包覆层压板在膜的平面方向上收缩。

7. 发明申请

US20110318602A1 Metal-Coated Polyimide Resin Substrate with Excellent Thermal Aging Resistance Properties 审中-公开
标题翻译：金属涂层聚酰亚胺树脂基材具有优异的耐热老化性能
公开(公告)号：US20110318602A1
公开(公告)日：2011-12-29
申请号：US13148708
申请日：2010-02-17
申请人： Taku Yoshida
发明人： Taku Yoshida
IPC分类号： B32B27/06 , B32B33/00
CPC分类号： H05K3/388 , C23C18/1651 , C23C18/2006 , C23C18/204 , C23C18/24 , C25D5/56 , H05K1/0346 , H05K3/181 , H05K3/381 , H05K2201/0154 , H05K2201/0344 , H05K2201/2063 , Y10T428/12535 , Y10T428/31721
摘要： [Object] To provide a metal-coated polyimide resin substrate that does not deteriorate the initial adhesion between the metal-coated polyimide resin film and the metal layer and has high adhesion after aging at 150° C. for 168 hours.[Solution] A metal-coated polyimide resin substrate in which a barrier layer is formed by a wet process after performing surface modification to one surface or both surfaces of a polyimide resin film by a wet process or a dry process or a combination thereof, a seed layer is thereafter formed by a wet process or a dry process, and a conductive film is formed on a surface layer thereof by a wet process; wherein, at the peeling surface on the conductive film layer side after the metal-coated polyimide resin substrate is subject to a 90-degree peel test, the thickness of a mixed layer of polyimide residue and barrier metal layer residue according to in-depth profiling with a time-of-flight secondary ion mass spectrometer (TOF-SIMS) is 2.60 nm or less based on Si sputter rate conversion, and peel strength retention after an aging test at 150° C. for 168 hours (peel strength after aging at 150° C. for 168 hours/initial peel strength) is 50% or higher.
摘要翻译：本发明提供一种金属包覆的聚酰亚胺树脂基板，其不会使金属包覆的聚酰亚胺树脂膜与金属层之间的初始粘合性劣化，并且在150℃下老化168小时后具有高粘附性。 [方案]一种金属涂覆的聚酰亚胺树脂基板，其中通过湿法或干法或其组合对聚酰亚胺树脂膜的一个表面或两个表面进行表面改性之后通过湿法形成阻挡层，然后通过湿法或干法形成种子层，并通过湿法在其表面层上形成导电膜; 其中，在金属涂覆的聚酰亚胺树脂基板进行90度剥离试验之后的导电膜层侧的剥离面上，根据深度图案，聚酰亚胺残留物和阻隔金属层残留物的混合层的厚度使用飞行时间次级离子质谱仪（TOF-SIMS），基于Si溅射速率转换为2.60nm以下，150℃下老化试验后的剥离强度保持168小时（老化后的剥离强度 150℃，168小时/初始剥离强度）为50％以上。

8. 发明授权

US08065794B2 Printed wiring board and its manufacturing method 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US08065794B2
公开(公告)日：2011-11-29
申请号：US12239306
申请日：2008-09-26
申请人： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
发明人： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
IPC分类号： H05K3/02 , H01K3/22
CPC分类号： H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.
摘要翻译：本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔并且可以实现高可靠性的导体连接而不退火。本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

9. 发明申请

US20090145652A1 PRINTED WIRING BOARD AND ITS MANUFACTURING METHOD 有权
标题翻译：印刷线路板及其制造方法
公开(公告)号：US20090145652A1
公开(公告)日：2009-06-11
申请号：US12239306
申请日：2008-09-26
申请人： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
发明人： Honchin En , Tohru Nakai , Takeo Oki , Naohiro Hirose , Kouta Noda
IPC分类号： C23C18/31 , C25D5/00 , H01B13/00 , B05D5/12 , C09D5/10
CPC分类号： H05K3/4644 , C23C18/1607 , C23C18/1653 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/405 , C23C28/00 , C23C28/023 , C23C28/42 , C25D3/38 , C25D5/022 , C25D5/18 , C25D5/34 , C25D7/123 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K3/0038 , H05K3/108 , H05K3/181 , H05K3/241 , H05K3/381 , H05K3/382 , H05K3/384 , H05K3/421 , H05K3/423 , H05K3/427 , H05K3/4602 , H05K3/4652 , H05K3/4661 , H05K2201/0215 , H05K2201/0344 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2201/0959 , H05K2201/096 , H05K2203/0353 , H05K2203/0723 , H05K2203/1476 , H05K2203/1492 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.
摘要翻译：本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔并且可以实现高可靠性的导体连接而不退火。本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

10. 发明授权

US06585904B2 Method for the manufacture of printed circuit boards with plated resistors 有权
公开(公告)号：US06585904B2
公开(公告)日：2003-07-01
申请号：US09784242
申请日：2001-02-15
申请人： Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
发明人： Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
IPC分类号： H01B1300
CPC分类号： H01C17/24 , H01C17/242 , H05K1/167 , H05K3/027 , H05K3/064 , H05K3/184 , H05K2201/0344 , H05K2203/0315 , H05K2203/107 , H05K2203/1105 , H05K2203/1453 , H05K2203/171
摘要： A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.

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