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1. 发明授权

US09277654B2 Composite polymer-metal electrical contacts 有权
标题翻译：复合聚合物 - 金属电接点
公开(公告)号：US09277654B2
公开(公告)日：2016-03-01
申请号：US13318369
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K1/16 , H05K1/11 , H05K7/10 , H05K7/12 , H05K3/32 , H01L23/498 , H01R12/52
CPC分类号： H05K3/325 , H01L23/49811 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/09701 , H01L2924/12044 , H01L2924/3011 , H01R12/52 , H05K2201/0133 , H05K2201/0311 , Y10T29/49224 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An array of composite polymer-metal contact members adapted to form solder free electrical connections with a first circuit member. The contact members include a resilient polymeric base layer and an array of metalized traces printed on selected portions of the base layer. Conductive plating is applied to the metalized layer to create an array of conductive paths. The resilient polymeric base layer, the metalized layer, and the conductive plating have an aggregate spring constant sufficient to maintain distal portions of the contact members in a cantilevered configuration and to form a stable electrical connection between the distal portions and the first circuit member solely by compressive engagement.
摘要翻译：一组复合聚合物 - 金属接触构件，适于与第一电路构件形成无焊料电连接。接触构件包括弹性聚合物基底层和印刷在基底层的选定部分上的金属化迹线阵列。将导电电镀施加到金属化层以形成导电路径阵列。弹性聚合物基层，金属化层和导电镀层具有足够的聚集弹簧常数，以使接触构件的远侧部分保持悬臂结构，并且仅在远侧部分和第一电路部件之间形成稳定的电连接压缩接合。

2. 发明授权

US09184145B2 Semiconductor device package adapter 有权
标题翻译：半导体器件封装适配器
公开(公告)号：US09184145B2
公开(公告)日：2015-11-10
申请号：US13643436
申请日：2011-04-25
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01L23/00 , H01L23/48 , H01R12/70 , H01R13/6474 , H01L23/552 , H05K3/32 , H01R13/6585 , H01L25/065 , H05K3/34
CPC分类号： H01L24/14 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2924/01029 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01R12/7076 , H01R13/6474 , H01R13/6585 , H01R2201/20 , H05K3/32 , H05K3/3436 , H05K2201/10378 , H05K2201/1059 , H05K2201/10734 , H05K2201/10962 , H01L2924/00
摘要： A semiconductor device packaged adapter for electrically coupling contacts on a first circuit member to contacts on a second circuit member. The adapter typically includes first and second substrates, each with arrays of terminals. Proximal ends of the first terminals on the first substrate are arranged to be soldered to the contacts on the first circuit member and proximal ends of the second terminals on the second substrate are arranged to be soldered to the contacts on the second circuit member. Complementary engaging structures located on distal ends of the first and second terminals engage to electrically and mechanically couple the first circuit member to the second circuit member.
摘要翻译：一种半导体器件封装适配器，用于将第一电路构件上的触点电耦合到第二电路构件上的触点。适配器通常包括第一和第二基板，每个具有端子阵列。第一基板上的第一端子的近端被布置成焊接到第一电路构件上的触点，并且第二基板上的第二端子的近端被布置成焊接到第二电路构件上的触点。位于第一和第二端子的远端上的互补接合结构接合以将第一电路构件电连接和机械耦合到第二电路构件。

3. 发明授权

US09093767B2 High performance surface mount electrical interconnect 有权
标题翻译：高性能表面贴装电气互连
公开(公告)号：US09093767B2
公开(公告)日：2015-07-28
申请号：US13879883
申请日：2011-11-29
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01R31/06 , H01R13/24 , H05K3/32 , H05K3/40 , H05K7/10 , H05K3/10 , H05K3/12 , H05K1/14
CPC分类号： H01R23/6813 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01R12/73 , H01R12/82 , H01R13/2457 , H01R13/2485 , H01R31/06 , H05K1/092 , H05K1/111 , H05K1/141 , H05K1/182 , H05K3/0094 , H05K3/10 , H05K3/1291 , H05K3/326 , H05K3/363 , H05K3/365 , H05K3/4007 , H05K3/4015 , H05K3/4092 , H05K3/425 , H05K3/4694 , H05K7/1076 , H05K2201/0397 , H05K2201/048 , H05K2201/09381 , H05K2201/09545 , H05K2201/09563 , H05K2201/09854 , H05K2201/10378 , H05K2201/10386 , H05K2201/2072 , H05K2201/209 , H05K2203/041 , H05K2203/1476 , Y10T29/49165 , H01L2224/45099 , H01L2924/00
摘要： A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. The electrical interconnect includes a socket substrate with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are bonded to the first surface of the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias are located in the openings that electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pad that are adapted to electrically and mechanically couple the electrical interconnect to the PCB.
摘要翻译：适于在BGA器件上的焊球和PCB之间提供界面的表面贴装电互连。电互连包括具有第一表面，第二表面和多个开口的插座基板，其尺寸和构造用于接收BGA器件上的焊球。多个导电接触片接合到插座衬底的第一表面，使得接触片上的接触尖端延伸到开口中。当焊球定位在开口中时，接触尖端与BGA器件电耦合。通孔位于开口中，其将接触片电耦合到位于插座衬底的第二表面附近的接触垫。焊球被接合到接触焊盘上，适于电连接和机械地将电互连件耦合到PCB。

4. 发明授权

US08987886B2 Copper pillar full metal via electrical circuit structure 有权
标题翻译：铜柱全金属通过电路结构
公开(公告)号：US08987886B2
公开(公告)日：2015-03-24
申请号：US13413724
申请日：2012-03-07
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01L23/52 , H01L23/498 , H01L21/48 , H01L21/768
CPC分类号： H01L23/49827 , G02B6/3608 , G02B6/4281 , H01L21/486 , H01L21/76831 , H01L23/3128 , H01L23/49822 , H01L23/60 , H01L24/13 , H01L24/48 , H01L25/16 , H01L2223/6627 , H01L2224/0401 , H01L2224/08235 , H01L2224/1132 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/48227 , H01L2224/48235 , H01L2224/81192 , H01L2924/00014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars.
摘要翻译：一种电互连，包括具有第一表面和第二表面的第一电路层。至少第一电介质层印刷在第一电路层的第一表面上以包括多个第一凹槽。导电材料沉积在多个第一凹槽中以形成电耦合到第一电路层并且大致垂直于第一电路层延伸的多个第一导电柱。至少第二电介质层印刷在第一电介质层上以包括与多个第一导电柱大致对准的多个第二凹部。导电材料沉积在多个第二凹槽中以形成电耦合到第一导电柱并平行延伸的多个第二导电柱。

5. 发明授权

US08955216B2 Method of making a compliant printed circuit peripheral lead semiconductor package 有权
标题翻译：制造兼容印刷电路外围引线半导体封装的方法
公开(公告)号：US08955216B2
公开(公告)日：2015-02-17
申请号：US13318181
申请日：2010-05-25
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K3/30 , H01L21/683 , H01L21/48 , H01L23/498 , H01L23/00 , H01L25/065 , H05K3/46
CPC分类号： H01L21/6835 , H01L21/4867 , H01L23/49822 , H01L23/4985 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L2221/68345 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K3/4664 , H05K3/4682 , Y10T29/4913 , Y10T29/49146 , Y10T29/49155 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A compliant printed circuit semiconductor package including a compliant printed circuit with at least a first dielectric layer selectively printed on a substrate with first recesses. A conductive material is printed in the first recesses to form contact members accessible along a first surface of the compliant printed circuit. At least one semiconductor device is located proximate the first surface of the compliant printed circuit. Wirebonds electrically couple terminals on the semiconductor device to the contact members. Overmolding material seals the semiconductor device and the wirebonds to the first surface of the compliant printed circuit. Contact pads on a second surface of the compliant printed circuit are electrically coupled to the contact members.
摘要翻译：一种兼容的印刷电路半导体封装，包括具有至少第一介电层的柔性印刷电路，所述第一介电层选择性地印刷在具有第一凹槽的在第一凹部中印刷导电材料以形成可沿顺应性印刷电路的第一表面接触的接触部件。至少一个半导体器件位于顺应印刷电路的第一表面附近。接线将半导体器件上的端子电耦合到接触构件。包覆成型材料将半导体器件和引线密封到兼容印刷电路的第一表面。柔性印刷电路的第二表面上的接触焊盘电耦合到接触构件。

6. 发明授权

US08618649B2 Compliant printed circuit semiconductor package 有权
标题翻译：符合印刷电路半导体封装
公开(公告)号：US08618649B2
公开(公告)日：2013-12-31
申请号：US13318263
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/82 , H01L23/49811 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/20 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15153 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025 , H05K1/185 , H01L2924/00
摘要： A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.
摘要翻译：用于至少一个半导体器件的封装以及用于制造封装的方法。至少一个电介质层被选择性地印刷在半导体器件的至少一部分上，形成与多个电端子对准的第一凹槽。在形成半导体器件上的接触部件的第一凹部中印刷导电材料。至少一个电介质层被选择性地印刷在封装的至少一部分上以产生对应于目标电路几何形状的多个第二凹部。导电材料印刷在第二凹槽的至少一部分中以产生电路几何形状。电路几何形状包括电耦合到半导体器件上的电端子的多个暴露端子。

7. 发明申请

US20130206468A1 ELECTRICAL INTERCONNECT IC DEVICE SOCKET 有权
标题翻译：电气互连IC器件插座
公开(公告)号：US20130206468A1
公开(公告)日：2013-08-15
申请号：US13880461
申请日：2011-12-05
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K1/02 , H05K3/40
CPC分类号： H05K1/0228 , H01R43/0256 , H05K1/0296 , H05K1/141 , H05K3/3436 , H05K3/3484 , H05K3/40 , H05K3/4046 , H05K2201/10378 , H05K2203/041 , Y10T29/49147
摘要： A surface mount electrical interconnect is disclosed that provides an interface between a PCB and solder balls of a BGA device. The electrical interconnect includes a socket substrate and a plurality of electrically conductive contact members. The socket substrate has a first layer with a plurality of openings configured to receive solder balls of the BGA device and has a second layer with a plurality of slots defined therethrough that correspond to the plurality of openings. The contact members may be disposed in the openings in the first layer and through the plurality of slots of the second layer of the socket substrate. The contact members can be configured to engage a top portion, a center diameter, and a lower portion of the solder ball of the BGA device. Each contact member electrically couples a solder ball on the BGA device to the PCB.
摘要翻译：公开了一种表面贴装电互连，其提供了PCB与BGA器件的焊球之间的界面。电互连包括插座衬底和多个导电接触构件。插座衬底具有第一层，其具有多个开口，其被配置为接收BGA器件的焊球，并且具有第二层，其中限定了多个槽，其对应于多个开口。接触构件可以设置在第一层中的开口中并且穿过插座衬底的第二层的多个槽中。接触构件可以构造成接合BGA装置的焊球的顶部，中心直径和下部。每个接触构件将BGA器件上的焊球电耦合到PCB。

8. 发明申请

US20120182035A1 BUMPED SEMICONDUCTOR WAFER OR DIE LEVEL ELECTRICAL INTERCONNECT 有权
标题翻译：保护半导体波形或电源电气互连
公开(公告)号：US20120182035A1
公开(公告)日：2012-07-19
申请号：US13413032
申请日：2012-03-06
申请人： JAMES RATHBURN
发明人： JAMES RATHBURN
IPC分类号： G01R31/20
CPC分类号： G01R31/2889
摘要： A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.
摘要翻译：探针组件，用作IC器件和测试台之间的端子之间的临时互连。探针组件包括布置在基板的第一表面上的多个突起凸块，其配置对应于IC器件上的端子。螺柱凸块包括适于临时与IC器件上的端子连接的形状。基板上的多个导电迹线使柱形突起与测试台电耦合。

9. 发明申请

US20120051016A1 SEMICONDUCTOR SOCKET 有权
标题翻译：半导体插座
公开(公告)号：US20120051016A1
公开(公告)日：2012-03-01
申请号：US13319158
申请日：2010-06-15
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K7/00 , H01R9/00 , H05K1/11
CPC分类号： H05K1/141 , H01R12/52 , H01R12/57 , H05K3/3436 , H05K2201/0311 , H05K2201/049 , H05K2201/10295 , H05K2201/10719 , Y10T29/49139 , Y10T29/49147
摘要： A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.
摘要翻译：一种半导体插座，包括具有从第一表面延伸到第二表面的多个通孔的基板。多个离散接触构件位于多个通孔中。多个接触构件各自包括可从第二表面接近的近端和在第一表面上方延伸的远端。至少一个电介质层与基板的第二表面结合，其凹部对应于目标电路几何形状。沉积在至少一部分凹陷中的导电材料以形成重新分布接触构件的近端的端子间距的导电迹线。

10. 发明申请

US20120049877A1 COMPLIANT PRINTED CIRCUIT PERIPHERAL LEAD SEMICONDUCTOR TEST SOCKET 有权
标题翻译：合格打印电路外围引线半导体测试插座
公开(公告)号：US20120049877A1
公开(公告)日：2012-03-01
申请号：US13318171
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R31/00 , H05K3/00
CPC分类号： G01R1/0483 , G01R1/0466 , H05K7/1061
摘要： A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.
摘要翻译：一个测试插座，用于在集成电路（IC）器件的端子和测试印刷电路板（PCB）上的接触焊盘之间提供临时互连。测试插座包括兼容印刷电路和插座外壳。柔性印刷电路包括至少一个柔性层，沿着第一主表面定位的多个第一接触构件，沿着第二主表面定位的多个第二接触构件，以及多个导电迹线，电耦合第一和第二接触会员柔性层被定位成将第一接触构件抵靠在IC器件上的端子上，并且第二接触构件抵抗测试PCB上的接触焊盘。插座壳体耦合到柔性印刷电路，使得第一接触构件位于插座壳体的凹部中，其尺寸设置成接收IC器件。

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