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1. 发明申请

US20100258927A1 Package-on-package interconnect stiffener 有权
标题翻译：封装在一起的互连加强筋
公开(公告)号：US20100258927A1
公开(公告)日：2010-10-14
申请号：US12384984
申请日：2009-04-10
申请人： Sanka Ganesan , Yosuke Kanaoka , Ram S. Viswanath , Rajasekaran Swaminathan , Robert M. Nickerson , Leonel R. Arane , John S. Guzek , Yoshihiro Tomita
发明人： Sanka Ganesan , Yosuke Kanaoka , Ram S. Viswanath , Rajasekaran Swaminathan , Robert M. Nickerson , Leonel R. Arane , John S. Guzek , Yoshihiro Tomita
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L23/488 , H01L21/50 , H01L23/3128 , H01L23/49833 , H01L23/562 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
摘要翻译：本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有与所述第二封装的SLI焊盘电连接的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘包。

2. 发明申请

US20160240949A1 LOW PROFILE ZERO/LOW INSERTION FORCE PACKAGE TOP SIDE FLEX CABLE CONNECTOR ARCHITECTURE 审中-公开
标题翻译：低配置零/低插入力封装顶部边缘电缆连接器架构
公开(公告)号：US20160240949A1
公开(公告)日：2016-08-18
申请号：US15135413
申请日：2016-04-21
申请人： Sanka Ganesan , Ram S. Viswanath
发明人： Sanka Ganesan , Ram S. Viswanath
IPC分类号： H01R12/79 , H05K1/14 , H01L23/367 , H01L23/498 , H01L23/00
CPC分类号： H01R12/79 , H01B7/04 , H01L23/3675 , H01L23/49811 , H01L23/49838 , H01L24/17 , H01L24/72 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01R12/62 , H05K1/142 , H05K1/147 , H05K3/361 , H05K2201/10318 , H05K2201/10325 , H05K2201/10424 , H05K2201/10674 , H05K2201/10681 , H05K2201/2009 , H01L2224/0401
摘要： An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
摘要翻译：介绍了一种集成电路封装。在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

3. 发明申请

US20150118870A1 INTEGRATED CIRCUIT CONNECTORS 有权
标题翻译：集成电路连接器
公开(公告)号：US20150118870A1
公开(公告)日：2015-04-30
申请号：US14065281
申请日：2013-10-28
申请人： Rajasekaran Swaminathan , Ram S. Viswanath , Sanka Ganesan , Gaurav Chawla , Joshua D. Heppner , Jeffory L. Smalley , Vijaykumar Krithivasan , David J. Llapitan , Neal E. Ulen , Donald T. Tran
发明人： Rajasekaran Swaminathan , Ram S. Viswanath , Sanka Ganesan , Gaurav Chawla , Joshua D. Heppner , Jeffory L. Smalley , Vijaykumar Krithivasan , David J. Llapitan , Neal E. Ulen , Donald T. Tran
IPC分类号： H01R12/71 , H01R43/00
CPC分类号： H05K7/10 , H01R12/00 , H01R12/716 , H01R13/2442 , H05K1/00 , Y10T29/49169
摘要： Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.
摘要翻译：描述了与集成电路（IC）连接器相关的实施例。在一些实施例中，IC组件可以包括IC封装衬底，中间构件和阳连接器。 IC封装基板可以在顶表面或底表面上具有第一信号触点，并且底表面可以具有用于与电路板上的插座耦合的第二信号触点。中间构件可以具有联接到第一信号触头的第一端和延伸超过侧表面的第二端。阳连接器可以设置在中间构件的第二端处，并且可以具有联接到中间构件的信号触点的信号触点。当阴连接器沿平行于中间构件的轴线的方向接合时，阳连接器可与母连接器配合。可以公开和/或要求保护其他实施例。

4. 发明申请

US20160183374A1 CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES 有权
标题翻译： CPU封装基板与可拆卸的存储器机械接口
公开(公告)号：US20160183374A1
公开(公告)日：2016-06-23
申请号：US14575775
申请日：2014-12-18
申请人： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
发明人： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
IPC分类号： H05K1/18 , H01R12/72 , H05K1/11 , H05K1/02 , H05K3/30 , H05K3/34
CPC分类号： H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
摘要翻译：公开了可配置的中央处理单元（CPU）封装基板。描述了包括处理设备接口的封装衬底。封装衬底还包括设置在封装衬底上的存储器件电接口。封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

5. 发明授权

US09324678B2 Low profile zero/low insertion force package top side flex cable connector architecture 有权
标题翻译：薄型零/低插入力封装顶端柔性电缆连接器架构
公开(公告)号：US09324678B2
公开(公告)日：2016-04-26
申请号：US13996498
申请日：2011-12-20
申请人： Sanka Ganesan , Ram S. Viswanath
发明人： Sanka Ganesan , Ram S. Viswanath
IPC分类号： H01L23/48 , H01L23/52 , H01L23/40 , H01L23/00 , H01R12/62 , H05K3/36 , H01L23/498 , H01B7/04 , H05K1/14
CPC分类号： H01R12/79 , H01B7/04 , H01L23/3675 , H01L23/49811 , H01L23/49838 , H01L24/17 , H01L24/72 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01R12/62 , H05K1/142 , H05K1/147 , H05K3/361 , H05K2201/10318 , H05K2201/10325 , H05K2201/10424 , H05K2201/10674 , H05K2201/10681 , H05K2201/2009 , H01L2224/0401
摘要： An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
摘要翻译：介绍了一种集成电路封装。在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

6. 发明申请

US20130292838A1 PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER 审中-公开
公开(公告)号：US20130292838A1
公开(公告)日：2013-11-07
申请号：US13939146
申请日：2013-07-10
申请人： Sanka Ganesan , Yosuke Kanaoka , Ram S. Viswanath , Rajasekaran Swaminathan , Robert M. Nickerson , Leonel R. Arana , John S. Guzek , Yoshihiro Tomita
发明人： Sanka Ganesan , Yosuke Kanaoka , Ram S. Viswanath , Rajasekaran Swaminathan , Robert M. Nickerson , Leonel R. Arana , John S. Guzek , Yoshihiro Tomita
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L23/488 , H01L21/50 , H01L23/3128 , H01L23/49833 , H01L23/562 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
摘要翻译：本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘包。

7. 发明授权

US08513792B2 Package-on-package interconnect stiffener 有权
标题翻译：封装在一起的互连加强筋
公开(公告)号：US08513792B2
公开(公告)日：2013-08-20
申请号：US12384984
申请日：2009-04-10
申请人： Sanka Ganesan , Yosuke Kanaoka , Ram S. Viswanath , Rajasekaran Swaminathan , Robert M. Nickerson , Leonel R. Arana , John S. Guzek , Yoshihiro Tomita
发明人： Sanka Ganesan , Yosuke Kanaoka , Ram S. Viswanath , Rajasekaran Swaminathan , Robert M. Nickerson , Leonel R. Arana , John S. Guzek , Yoshihiro Tomita
IPC分类号： H01L23/02 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/488 , H01L21/50 , H01L23/3128 , H01L23/49833 , H01L23/562 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
摘要翻译：本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘包。

8. 发明授权

US09129958B2 3D integrated circuit package with window interposer 有权
标题翻译：具有窗口插入器的3D集成电路封装
公开(公告)号：US09129958B2
公开(公告)日：2015-09-08
申请号：US13995917
申请日：2011-12-22
申请人： Debendra Mallik , Ram S. Viswanath , Sriram Srinivasan , Mark T. Bohr , Andrew W. Yeoh , Sairam Agraharam
发明人： Debendra Mallik , Ram S. Viswanath , Sriram Srinivasan , Mark T. Bohr , Andrew W. Yeoh , Sairam Agraharam
IPC分类号： H01L23/48 , H01L23/498 , H01L23/13 , H01L25/065
CPC分类号： H01L23/49838 , H01L23/13 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L25/0652 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06555 , H01L2225/06562 , H01L2924/1461 , H01L2924/15151 , H01L2924/15311 , H01L2924/00
摘要： 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
摘要翻译：描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。例如，半导体封装包括衬底。顶部半导体管芯设置在衬底上方。具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。在另一示例中，半导体封装包括衬底。顶部半导体管芯设置在衬底上方。插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

9. 发明授权

US06493223B1 Computer utilizing refrigeration for cooling 失效
标题翻译：计算机利用制冷冷却
公开(公告)号：US06493223B1
公开(公告)日：2002-12-10
申请号：US09606840
申请日：2000-06-28
申请人： Ram S. Viswanath , Hong Xie , Robert Sankman
发明人： Ram S. Viswanath , Hong Xie , Robert Sankman
IPC分类号： H05K720
CPC分类号： G06F1/20 , G06F2200/201
摘要： The invention provides a computer with refrigeration. The computer has a housing, a processor, a refrigeration loop and a fan. The processor is located within the housing at a location distant from an air inlet into the housing. The refrigeration loop includes a compressor, a condenser, and expansion valve and an evaporator located in line one after the other. The evaporator is near the air inlet. The fan causes movement of air through the housing. The air passes over the evaporator to cool the air and the processor is primarily cooled by the air.
摘要翻译：本发明提供一种具有制冷的计算机。计算机具有外壳，处理器，制冷回路和风扇。处理器位于壳体内的远离进入壳体的空气入口的位置。制冷回路包括压缩机，冷凝器，膨胀阀和蒸发器，一个接一个地排成一列。蒸发器靠近进气口。风扇引起空气流过外壳。空气通过蒸发器以冷却空气，处理器主要由空气冷却。

10. 发明授权

US06072322A Thermally enhanced test socket 失效
标题翻译：热增强测试插座
公开(公告)号：US06072322A
公开(公告)日：2000-06-06
申请号：US631
申请日：1997-12-30
申请人： Ram S. Viswanath , Martin M. Maxwell
发明人： Ram S. Viswanath , Martin M. Maxwell
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R31/2863 , G01R1/0483 , G01R31/2874
摘要： A test socket having a heat slug for removing heat from an electronic device positioned within the socket. In one embodiment the test socket includes a burn-in board electrically coupled to a test unit that generates a series of test signals to test the performance of the electronic device. Examples of electronic devices that can be tested by the test socket are integrated circuit packages such as tape carrier packages (TCP), ball grid arrays (BGA), pin grid arrays (PGA), land grid arrays (LGA), and other packages. The integrated circuit package is positioned within the socket which electrically connects the package to a printed circuit board, such as a burn-in board. The test socket includes an opening in which a heat slug is disposed. The heat slug has a contact surface that contacts the integrated circuit device under test. In another embodiment, the socket includes a lid having a heat slug attached to the lid, which heat slug has a contact surface that contacts an integrated circuit device under test.
摘要翻译：一种测试插座，其具有用于从位于插座内的电子设备移除热量的热塞。在一个实施例中，测试插座包括电耦合到测试单元的老化板，其生成一系列测试信号以测试电子设备的性能。可以通过测试插座测试的电子设备的例子是集成电路封装，例如带状载体封装（TCP），球栅阵列（BGA），引脚格栅阵列（PGA），光栅阵列（LGA）和其它封装。集成电路封装位于插座内，该插座将封装电连接到印刷电路板，例如老化板。测试插座包括其中设置有热塞的开口。散热片具有与待测集成电路器件接触的接触表面。在另一个实施例中，插座包括具有附接到盖子的散热片的盖子，该热塞具有接触被测试集成电路器件的接触表面。

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