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61. 发明申请

US20020075980A1 PLL/DLL dual loop data synchronization utillizing a granular FIFO fill level indicator 有权
标题翻译： PLL / DLL双循环数据同步使粒度FIFO填充级别指示符充满
公开(公告)号：US20020075980A1
公开(公告)日：2002-06-20
申请号：US10029709
申请日：2001-12-20
发明人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
IPC分类号： H04L007/00 , H04L025/00 , H04L025/40 , H03D003/24
CPC分类号： G06F5/12 , G06F2205/061 , H03L7/081 , H03L7/087 , H04J3/047 , H04J3/062 , H04J3/0685
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。特别地，提供了一种使用粒度FIFO填充水平指示符的双循环数据同步的系统和方法。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，它表示FIFO的填充级别。该DLL的粒状FIFO填充电平指示器为移相器提供输入以相应地调整PLL的频率。因此，可以控制数据输入速率的频率，并且可以保持FIFO的恒定填充电平。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

62. 发明授权

US06247072B1 Real-time data rate matching across a medium 失效
标题翻译：跨媒介的实时数据速率匹配
公开(公告)号：US06247072B1
公开(公告)日：2001-06-12
申请号：US09013866
申请日：1998-01-27
申请人： Scott Firestone
发明人： Scott Firestone
IPC分类号： G06F1300
CPC分类号： H04N21/431 , G06F5/06 , G06F5/12 , G06F2205/061 , G06F2205/126 , H04N21/23406 , H04N21/2381 , H04N21/4307 , H04N21/44004 , H04N21/440281 , H04N21/6437
摘要： Apparatus and methods for matching data rates is useful for a receiver receiving real-time data over a medium. Implementations feature a process establishing a buffer in a receiver; receiving source data from a source having a nominal source data rate, the received source data arriving at an incoming data rate that differs from time-to-time from the nominal source data rate; filling the buffer with source data as it is received at the incoming data rate and emptying the buffer to provide data for consumption in real time at a consumption data rate; setting a rate-matching factor M, the factor M affecting the rate at which the buffer is emptied; and tracking the level of data in the buffer and resetting the value of M to increase the rate at which the buffer is emptied when the buffer fills above a target range, and resetting the value of M to decrease the rate at which the buffer is emptied when the buffer empties below a target range.
摘要翻译：用于匹配数据速率的装置和方法对于在介质上接收实时数据的接收器是有用的。实现特征在于在接收器中建立缓冲器的过程; 从具有标称源数据速率的源接收源数据，所接收的源数据以与标称源数据速率的时间不同的输入数据速率到达; 在传入数据速率接收到源数据时填充缓冲器，并将缓冲器清空以消耗数据速率实时提供消耗数据; 设置速率匹配因子M，影响缓冲器清空速率的因子M; 并且跟踪缓冲器中的数据级别并重置M的值以在缓冲器填满目标范围时提高缓冲器被清空的速率，并且重置M的值以降低缓冲器被清空的速率当缓冲液清空到目标范围以下时。

63. 发明授权

US06202164B1 Data rate synchronization by frame rate adjustment 失效
标题翻译：数据速率同步通过帧速率调整
公开(公告)号：US06202164B1
公开(公告)日：2001-03-13
申请号：US09109822
申请日：1998-07-02
申请人： Dale E. Gulick
发明人： Dale E. Gulick
IPC分类号： G06F1300
CPC分类号： H04L12/40058 , G06F1/08 , G06F5/06 , G06F13/423 , G06F2205/061 , H04L12/40123 , H04N5/232
摘要： A master isochronous clock structure wherein a frame-rate clock of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clocks signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data. In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data. In one embodiment, the level of data in a data buffer is used to synchronize the clock of a video camera. In another embodiment, the level of data in a data buffer is used to synchronize a clock of a telephony codec.
摘要翻译：一种主同步时钟结构，其中多个数据总线的帧速率时钟与主时钟信号同步。主时钟信号可以从计算机系统内的现有时钟信号或从外部源接收的数据中导出。主时钟信号也可由操作系统调度器用于调度生成或消耗同步数据块的任务。在替代实施例中，测量器件时钟信号相对于主时钟信号的漂移并用于同步器件时钟信号。例如，机制可以监视数据缓冲器中的数据级别。数据缓冲器中的数据电平是产生数据的时钟与消耗数据的时钟之间的漂移的量度。基于缓冲器中的数据级别，提供同步信息以同步产生和消耗数据的时钟信号的速率。在一个实施例中，使用数据缓冲器中的数据级别来同步摄像机的时钟。在另一个实施例中，数据缓冲器中的数据级别用于同步电话编解码器的时钟。

64. 发明授权

US6128749A Cross-clock domain data transfer method and apparatus 有权
标题翻译：跨时钟域数据传输方法和装置
公开(公告)号：US6128749A
公开(公告)日：2000-10-03
申请号：US186046
申请日：1998-11-03
申请人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
发明人： David J. McDonnell , Andrew M. Volk , Michael W. Williams
IPC分类号： G06F1/04 , G06F12/00 , G06F13/00 , H04L12/403 , H04L12/54
CPC分类号： G06F5/06 , G06F13/1689 , G06F2205/061
摘要： An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously been loaded into the storage circuit and that will not be output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.
摘要翻译：一种用于在时钟域之间传送信息单元的装置和方法。在第一时钟域的每个周期期间，将相应的N个信息单元从第一时钟域中的输出电路加载到第二时钟域中的存储电路中。每一组N个单元由输出电路选择，包括（1）先前已经被加载到存储电路中的信息单元，并且在存储电路装载下一组 N个信息单元，以及（2）尚未加载到存储电路中的补充信息单元。

65. 发明授权

US5553041A Disc data reproducing apparatus and signal processing unit for preventing underflow and overflow 失效
标题翻译：光盘数据再现装置和用于防止下溢和溢出的信号处理单元
公开(公告)号：US5553041A
公开(公告)日：1996-09-03
申请号：US419272
申请日：1995-04-10
申请人： Jun Inagawa , Masahide Nagumo , Kunihiko Kodama
发明人： Jun Inagawa , Masahide Nagumo , Kunihiko Kodama
IPC分类号： G11B7/00 , G06F5/06 , G11B7/005 , G11B7/09 , G11B19/02 , G11B19/28 , G11B20/10 , G11B20/14 , H01L27/10
CPC分类号： G11B20/10527 , G06F5/06 , G11B19/02 , G11B20/10 , G06F2205/061 , G11B2020/10814 , G11B2020/10824 , G11B7/0946
摘要： An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from going overflow/underflow. Writing information data read from the disc to the buffer memory is performed in synchronism with a reproduction stage clock signal, and reading from the buffer memory is in synchronism with a signal processing stage clock. The signal processing stage clock for reading information data from the buffer memory is changed in accordance with the amount of information data stored in the buffer memory for preventing interruptions in data reproduction.
摘要翻译：一种用于再现存储在盘上的数据以防止缓冲存储器上溢/下溢的装置，信号处理电路和方法。将从盘读取的信息数据写入缓冲存储器是与再现级时钟信号同步执行的，并且从缓冲存储器读取与信号处理级时钟同步。用于从缓冲存储器读取信息数据的信号处理级时钟根据存储在缓冲存储器中的用于防止数据再现中断的信息数据量而改变。

66. 发明授权

US5486784A Method and device for generation of clock signals 失效
标题翻译：用于产生时钟信号的方法和装置
公开(公告)号：US5486784A
公开(公告)日：1996-01-23
申请号：US346915
申请日：1994-11-23
申请人： Karl O. Eriksson
发明人： Karl O. Eriksson
IPC分类号： G06F5/06 , H04J3/06 , H04N21/43 , H04N21/44 , H03K5/01
CPC分类号： H04N21/4305 , G06F5/06 , H04J3/0632 , H04N21/44004 , G06F2205/061
摘要： A method and a device for regenerating clock rate information in which data is intermediately stored in a memory to which the data is read at a first rate and out of which the data is read at a second rate. The difference between two levels of the amount of data stored in the memory is determined, after which the difference is compared with a reference value. The result from the comparison affects the second rate so that, at subsequent measurements of the difference, the difference between it and the reference value shall decrease.
摘要翻译：一种用于再生时钟速率信息的方法和装置，其中数据被中间存储在以第一速率读取数据的存储器中，并且以第二速率读出数据。确定存储在存储器中的数据量的两个电平之间的差异，之后将差值与参考值进行比较。比较的结果影响第二速率，使得在差异的后续测量中，其与参考值之间的差异将减小。

67. 发明授权

US5367638A Digital data processing circuit with control of data flow by control of the supply voltage 失效
标题翻译：数字数据处理电路通过控制电源电压控制数据流
公开(公告)号：US5367638A
公开(公告)日：1994-11-22
申请号：US951520
申请日：1992-09-25
申请人： Cornelis Niessen , Cornelis H. van Berkel
发明人： Cornelis Niessen , Cornelis H. van Berkel
IPC分类号： G06F1/26 , G06F1/32 , G06F5/06 , G06F13/38 , G06F13/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： Digital data processing electronic circuitry based on self-timed elements. The operating speed of the electronic circuitry is determined by its power supply voltage. Moreover, a buffer is connected either to the input or to the output of the electronic circuitry. A filling degree signal from the buffer is fed back to a control input of a power supply voltage controller for the electronic circuitry. In this way the supply voltage of the electronic circuitry is adjusted to control the data flow in such a way that the buffer tends not to fill up or to become empty.
摘要翻译：基于自定时元素的数字数据处理电子电路。电子电路的工作速度由其电源电压决定。此外，缓冲器连接到电子电路的输入端或输出端。来自缓冲器的填充度信号被反馈到用于电子电路的电源电压控制器的控制输入。以这种方式，调整电子电路的电源电压以控制数据流，使得缓冲器倾向于不填充或变空。

68. 发明授权

US5339338A Apparatus and method for data desynchronization 失效
标题翻译：用于数据去同步的装置和方法
公开(公告)号：US5339338A
公开(公告)日：1994-08-16
申请号：US957223
申请日：1992-10-06
申请人： Paul M. Elliott
发明人： Paul M. Elliott
IPC分类号： G06F1/03 , G06F5/10 , H04J3/06 , H04L7/00
CPC分类号： G06F5/10 , G06F1/0328 , H04J3/0626 , G06F2101/04 , G06F2205/061
摘要： Apparatus and a method desynchronizes data by providing a high resolution FIFO depth measurement. A numerically controlled oscillator is combined with a FIFO memory to implement a variable frequency transmit clock signal having virtually unlimited frequency and phase resolution.
摘要翻译：设备和方法通过提供高分辨率FIFO深度测量来同步数据。数字振荡器与FIFO存储器组合以实现具有实际上无限频率和相位分辨率的可变频率发射时钟信号。

69. 发明授权

US08908719B2 Clock rate controller and method thereof and electronic device thereof 有权
标题翻译：时钟速率控制器及其方法及其电子设备
公开(公告)号：US08908719B2
公开(公告)日：2014-12-09
申请号：US13713017
申请日：2012-12-13
申请人： C-Media Electronics Inc.
发明人： Jung-Fu Liao , Hung-Chi Huang
IPC分类号： H04J3/06 , G06F5/06 , G06F13/40
CPC分类号： H04L41/08 , G06F5/06 , G06F5/12 , G06F13/40 , G06F2205/061 , H04J3/0635 , H04L41/0816 , H04N5/0736
摘要： An exemplary embodiment of the present disclosure illustrates a clock rate control method. Firstly, a usage of a first input first output (FIFO) buffer in an electronic device is detected. Then, whether the usage falls within a first specific interval is determined, wherein the first specific interval has a first upper limit value and a first lower limit value. When the usage is larger than the first upper limit value, a clock rate of the inner device of the electronic device is increased; when the usage is less than the first lower limit value, the clock rate is decreased.
摘要翻译：本公开的示例性实施例示出了时钟速率控制方法。首先，检测电子设备中的第一输入第一输出（FIFO）缓冲器的使用。然后，确定使用是否在第一特定间隔内，其中第一特定间隔具有第一上限值和第一下限值。当使用量大于第一上限值时，电子设备的内部设备的时钟速率增加; 当使用量小于第一下限值时，时钟速率降低。

70. 发明授权

US08843686B1 Processor management using a buffer 有权
标题翻译：处理器管理使用缓冲区
公开(公告)号：US08843686B1
公开(公告)日：2014-09-23
申请号：US13598282
申请日：2012-08-29
申请人： Ting Li Chan , Fredarico E. Dutton
发明人： Ting Li Chan , Fredarico E. Dutton
IPC分类号： G06F13/36
CPC分类号： G06F5/12 , G06F1/3209 , G06F1/3237 , G06F1/3287 , G06F2205/061 , G06F2205/126 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.
摘要翻译：在一个实施例中，一种装置包括缓冲器，多个处理器和处理器控制模块。处理器控制模块至少部分地基于存储在缓冲器中的数据的量来管理多个处理器用于处理来自缓冲器的数据。

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