专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07573915B1 Method and apparatus for transporting network management information in a telecommunications network 有权
标题翻译：用于在电信网络中传送网络管理信息的方法和装置
公开(公告)号：US07573915B1
公开(公告)日：2009-08-11
申请号：US09727905
申请日：2000-11-30
申请人： Charles Scott Roberson , Paul M. Elliott , Phu Son Le
发明人： Charles Scott Roberson , Paul M. Elliott , Phu Son Le
IPC分类号： H04B7/212 , H04J3/16 , H04J3/22 , G06F15/173
CPC分类号： H04J3/12 , H04J2203/0058 , H04L41/00 , H04L41/0213 , H04L41/022
摘要： Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.
摘要翻译：包含在接收帧的第一组字节位置中的网络管理信息（NMI）被重定位到另一帧的第二组字节位置。然后，NMI通过网络元件使用第二组字节位置传输，直到NMI被传输到可以理解NMI的兼容网络元件。此时，NMI被重新定位回去往兼容网络元件的帧的第一组字节位置。将NMI从第一组字节位置重新定位到第二组字节位置允许NMI通过不兼容的网络元件透明传输。

2. 发明授权

US06349092B1 BLSR node extension 有权
标题翻译： BLSR节点扩展
公开(公告)号：US06349092B1
公开(公告)日：2002-02-19
申请号：US09192975
申请日：1998-11-16
申请人： Patrick R. Bisson , Paul M. Elliott , Kate B. Amon , Anurag Nigam , Phu S. Le
发明人： Patrick R. Bisson , Paul M. Elliott , Kate B. Amon , Anurag Nigam , Phu S. Le
IPC分类号： H04L1228
CPC分类号： H04J3/085 , H04J2203/0042 , H04J2203/0051 , H04J2203/006
摘要： The present invention provides a method and structure for allowing more than 16 nodes to be configured in a single SONET BLSR network by utilizing unused portions of the transport overhead of an STS-N frame to expand the node identification field from 4 bits to 8 bits, thereby allowing up to 256 nodes to be present on a single ring.
摘要翻译：本发明提供一种方法和结构，用于通过利用STS-N帧的传输开销的未使用部分，将单个SONET BLSR网络中的16个节点配置为将节点识别字段从4位扩展到8位，从而允许在单个环上存在多达256个节点。

3. 发明授权

US5751724A Demultiplexer for a multi-bitline bus 失效
标题翻译：用于多位线总线的解复用器
公开(公告)号：US5751724A
公开(公告)日：1998-05-12
申请号：US606054
申请日：1996-02-23
申请人： Paul M. Elliott
发明人： Paul M. Elliott
IPC分类号： G06F13/40 , H03M9/00 , H04J3/04
CPC分类号： H03M9/00 , G06F13/4018
摘要： A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit parallel output at a second clock rate. An intermediary stage (14) receives the first n-bit parallel output and generates a second n-bit parallel output at the second clock rate. The first n-bit parallel output corresponds to a different portion of an m-bit section than the second n-bit parallel output. An output stage (16) receives the first n-bit parallel output from the input stage (12) and the second n-bit parallel output from the intermediary stage (14). The output stage (10) places the first n-bit parallel output onto an output bus (36) having a width of m-bitlines at an earlier instance in time than the placement of the second n-bit parallel output.
摘要翻译：解复用器（10）包括输入级（12），其以第一时钟速率接收具有多个m位部分的串行数据流。输入级以第二时钟速率将每个m位部分的连续n位部分转换为第一n位并行输出。中间级（14）接收第一n位并行输出并以第二时钟速率产生第二n位并行输出。第一n位并行输出对应于m位部分与第二n位并行输出的不同部分。输出级（16）接收来自输入级（12）的第一n位并行输出和来自中间级（14）的第二n位并行输出。输出级（10）将第一n比特并行输出放置在时间上比第二n位并行输出的放置的时间早的m位线宽度的输出总线（36）上。

4. 发明授权

US5521534A Numerically controlled oscillator for generating a digitally represented sine wave output signal 失效
标题翻译：用于产生数字表示的正弦波输出信号的数控振荡器
公开(公告)号：US5521534A
公开(公告)日：1996-05-28
申请号：US492927
申请日：1995-06-21
申请人： Paul M. Elliott
发明人： Paul M. Elliott
IPC分类号： G06F1/03 , H03B28/00 , H03B1/00
CPC分类号： G06F1/0335 , H03B28/00
摘要： A numerically controlled oscillator (10) includes a difference engine (12) that receives a numerator signal (14) and a numerator minus denominator signal (16). The numerator signal (14) and the numerator minus denominator signal (16) represent constant input values for a desired fractional relationship between a sine wave output signal (34) and a sample clock input signal (20) of numerically controlled oscillator (10). The difference engine (12) generates a difference output signal (18) that is received by a phase adder (22) for adding either a one or a zero to a combination of the delta phase input signal (24) and a phase accumulator output signal (26). The difference engine (12) optimally distributes ones and zeros so as to minimize phase jitter in the output signal (34).
摘要翻译：数控振荡器（10）包括接收分子信号（14）和分子负分母信号（16）的差分引擎（12）。分子信号（14）和分子负分母信号（16）表示正弦波输出信号（34）和数控振荡器（10）的采样时钟输入信号（20）之间的期望的分数关系的恒定输入值。差分引擎（12）产生差分输出信号（18），该差分输出信号（18）由相位加法器（22）接收，用于将一个或一个零加到增量相位输入信号（24）和相位累加器输出信号（26）。差分引擎（12）最佳地分配零和零以便最小化输出信号（34）中的相位抖动。

5. 发明授权

US6049541A Distributed telecommunications switching system and method 失效
标题翻译：分布式电信交换系统及方法
公开(公告)号：US6049541A
公开(公告)日：2000-04-11
申请号：US985387
申请日：1997-12-04
申请人： Daniel J. Kerns , Paul M. Elliott , Dieter H. Nattkemper
发明人： Daniel J. Kerns , Paul M. Elliott , Dieter H. Nattkemper
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/40
CPC分类号： H04L49/3081 , H04Q11/0478 , H04L2012/5605 , H04L2012/561 , H04L2012/5615 , H04L2012/5625 , H04L2012/5651
摘要： A distributed telecommunications switching system (100) is disclosed. The system includes a controller (140) that generates and transmits a cell stream with a plurality of reserved cells. A first switching subsystem (104) in communication with the controller (140) receives the cell stream and a first plurality of cells. The first switching subsystem (104) identifies the reserved cells in the cell stream and replaces selected ones of the reserved cells with selected ones of the first plurality of cells to produce a modified cell stream. The modified cell stream is transmitted to a second switching subsystem (102).
摘要翻译：公开了一种分布式电信交换系统（100）。该系统包括产生并发送具有多个保留小区的小区流的控制器（140）。与控制器（140）通信的第一交换子系统（104）接收小区流和第一多个小区。第一交换子系统（104）识别小区流中的保留小区，并且用第一多个小区中的选定小区替换保留小区中的所选小区以产生修改的小区流。经修改的小区流被传送到第二交换子系统（102）。

6. 发明授权

US5367476A Finite impulse response digital filter 失效
标题翻译：有限脉冲响应数字滤波器
公开(公告)号：US5367476A
公开(公告)日：1994-11-22
申请号：US32931
申请日：1993-03-16
申请人： Paul M. Elliott
发明人： Paul M. Elliott
IPC分类号： H03H17/02 , H03H17/06 , G06F15/31
CPC分类号： H03H17/06 , H03H17/0225 , H03H2218/085
摘要： A finite impulse response filter (10) incorporates a two input data multiplexer (12) and a series of delay registers (18, 20, and 22) for processing input samples off an input data line (14). The data multiplexer (12) selects between a feedback sample generated at the last delay register (22) and an input sample received on the input data line (14). A multiplier (24) combines a coefficient as selected by a coefficient multiplexer (26) with the selected sample to drive an adder (28). The adder (28) sums sequential products from the multiplexer (24) to drive an accumulator register (30). The accumulator register (30) provides the adder (28) with the sum of products feedback in order that the adder (28) may sum successive products together. At the completion of a cycle, the data multiplexer (12) selects a new input sample off the input data line (14) and the adder (28) to accumulator register (30) combination is reset through a zero adjust generator (32).
摘要翻译：有限脉冲响应滤波器（10）包括两个输入数据多路复用器（12）和一系列用于处理输入数据线（14）的输入采样的延迟寄存器（18,20和22）。数据多路复用器（12）在最后延迟寄存器（22）产生的反馈样本与在输入数据线（14）上接收的输入样本之间进行选择。乘法器（24）将由系数多路复用器（26）选择的系数与所选择的采样相结合，以驱动加法器（28）。加法器（28）将来自多路复用器（24）的顺序乘积相加以驱动累加器寄存器（30）。累加器寄存器（30）为加法器（28）提供乘积和的反馈，以便加法器（28）可以将连续的乘积相加在一起。在一个周期完成时，数据多路复用器（12）从输入数据线（14）中选择一个新的输入采样，并且加法器（28）到累加器寄存器（30）的组合通过零点调整发生器（32）复位。

7. 发明申请

US20090154501A1 Method and Apparatus For Transporting Network Management Information In a Telecommunications Network 有权
标题翻译：用于在电信网络中传送网络管理信息的方法和装置
公开(公告)号：US20090154501A1
公开(公告)日：2009-06-18
申请号：US12370455
申请日：2009-02-12
申请人： Charles Scott Roberson , Paul M. Elliott , Phu Son Le
发明人： Charles Scott Roberson , Paul M. Elliott , Phu Son Le
IPC分类号： H04J3/00
CPC分类号： H04J3/12 , H04J2203/0058 , H04L41/00 , H04L41/0213 , H04L41/022
摘要： Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.
摘要翻译：包含在接收帧的第一组字节位置中的网络管理信息（NMI）被重定位到另一帧的第二组字节位置。然后，NMI通过网络元件使用第二组字节位置传输，直到NMI被传送到可以理解NMI的兼容网络元件。此时，NMI被重新定位回去往兼容网络元件的帧的第一组字节位置。将NMI从第一组字节位置重新定位到第二组字节位置允许NMI通过不兼容的网络元件透明传输。

8. 发明授权

US6127863A Efficient fractional divider 有权
$Efficient fractional divider$
标题翻译：高效分数分频器
公开(公告)号：US6127863A
公开(公告)日：2000-10-03
申请号：US282387
申请日：1999-03-31
申请人： Paul M. Elliott
发明人： Paul M. Elliott
IPC分类号： G06F7/62 , H03K21/00
CPC分类号： G06F7/62
摘要： In accordance with the invention, a method and structure are provided for obtaining a ratio of M/(2.sup.N +K) by feeding various carry-out (and/or complemented carry-out) signals from full-adders back to various frequency control inputs of the full-adders to modify the denominator of the division ratio. By doing this, K additional or fewer counts are accumulated during each cycle. Thus, the denominator can be changed from 2.sup.N to 2.sup.N +K, where K can be either positive or negative to obtain the desired M/(2.sup.N +K) ratio.
摘要翻译：根据本发明，提供了一种方法和结构，用于通过将各种进位（和/或补码进位）信号从全加器馈送回各种频率控制输入来获得M /（2N + K）的比率的全加法器来修改分母比的分母。通过这样做，在每个周期内累积K个额外的或更少的计数。因此，分母可以从2N改变为2N + K，其中K可以是正或负，以获得所需的M /（2N + K）比。

9. 发明授权

US07929573B2 Method and apparatus for transporting network management information in a telecommunications network 有权
标题翻译：用于在电信网络中传送网络管理信息的方法和装置
公开(公告)号：US07929573B2
公开(公告)日：2011-04-19
申请号：US12370455
申请日：2009-02-12
申请人： Charles Scott Roberson , Paul M. Elliott , Phu Son Le
发明人： Charles Scott Roberson , Paul M. Elliott , Phu Son Le
IPC分类号： H04B7/212 , H04J3/16 , H04J3/22 , G06F15/173
CPC分类号： H04J3/12 , H04J2203/0058 , H04L41/00 , H04L41/0213 , H04L41/022
摘要： Network management information (NMI) contained in a first set of byte locations of a received frame is relocated to a second set of byte locations of another frame. The NMI is then transported through network elements using the second set of byte locations until the NMI is to be transported to a compatible network element, which can understand the NMI. At which time, the NMI is relocated back to the first set of byte locations of frames destined for the compatible network element. The relocation of the NMI from a first set of byte locations to a second set of byte locations allows the NMI to be transparently transported through incompatible network elements.
摘要翻译：包含在接收帧的第一组字节位置中的网络管理信息（NMI）被重定位到另一帧的第二组字节位置。然后，NMI通过网络元件使用第二组字节位置传输，直到NMI被传送到可以理解NMI的兼容网络元件。此时，NMI被重新定位回去往兼容网络元件的帧的第一组字节位置。将NMI从第一组字节位置重新定位到第二组字节位置允许NMI通过不兼容的网络元件透明传输。

10. 发明授权

US5497405A Open loop desynchronizer 失效
标题翻译：开环去同步器
公开(公告)号：US5497405A
公开(公告)日：1996-03-05
申请号：US87846
申请日：1993-07-01
申请人： Paul M. Elliott , Fredrik Nordling
发明人： Paul M. Elliott , Fredrik Nordling
IPC分类号： H04J3/07 , H04L7/00
CPC分类号： H04J3/076
摘要： An open loop desynchronizer (10) includes a demapper (12) that reads asynchronous data from a synchronous channel (14) and writes this data to a first in first out buffer (18). The demapper (12) decodes deviations from a nominal stuff bit rate that indicates whether fewer or more stuff bits than data bits are needed on the synchronous channel (14) and generates a frequency deviation control signal (20) therefrom. The frequency deviation control signal (20) drives a digital filter (22) and a numerically controlled oscillator (24). The digital filter (22) and numerically controlled oscillator (24) generate a transmit clock (26) that tracks the asynchronous payload rate according to unit pulses on the frequency deviation control signal (20). The first in first out buffer (18) transmits the asynchronous data over a transmit data line (28) according to the asynchronous payload rate generated on the transmit clock (26).
摘要翻译：开环去同步器（10）包括从同步信道（14）读取异步数据并将该数据写入到先进先出缓冲器（18）中的解映射器（12）。解映射器（12）解码与标称填充比特率的偏差，其指示在同步信道（14）上是否需要比数据比特少的或更多的填充比特，并从其生成频率偏差控制信号（20）。频率偏差控制信号（20）驱动数字滤波器（22）和数控振荡器（24）。数字滤波器（22）和数控振荡器（24）产生根据频率偏差控制信号（20）上的单位脉冲跟踪异步有效载荷速率的传输时钟（26）。第一个先出缓冲器（18）根据传输时钟（26）上产生的异步有效载荷速率，通过发送数据线（28）发送异步数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式