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1. 发明授权

US5005136A Silicon-compiler method and arrangement 失效
标题翻译：硅编译方法和布置
公开(公告)号：US5005136A
公开(公告)日：1991-04-02
申请号：US156392
申请日：1988-02-16
申请人： Cornelis H. Van Berkel , Ronald W. J. J. Saeijs , Cornelis Niessen
发明人： Cornelis H. Van Berkel , Ronald W. J. J. Saeijs , Cornelis Niessen
IPC分类号： G06F9/45 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A silicon-compilation method, a silicon-compiler arrangement, an abstract-circuit synthesis module usable in such arrangement, a machine-generated abstract circuit produced by such module, an electronic circuit generated by such method and a reset-free circuit produced by such arrangement. There are described a method and arrangement for silicon compilation. First, an algorithmic procedure to be executed by the electronic circuit is expressed in an imperative concurrent language. This, under execution of lexical, syntactic and semantic analysis is converted to a structure tree as an abstract representation of said procedure. This structure tree then is converted into an abstract circuit, wherein each basic component is a program module and each abstract channel corresponds to a program channel. Thereafter, the abstract circuit is converted into a concrete circuit, while obeying timing-organization constraints, circuitry-type constraints and technology constraints. Finally, the concrete circuit is converted into a very large-scale integrated-circuit layout.

2. 发明授权

US07274390B2 Device for parallel data processing, and camera system comprising such a device 有权
标题翻译：用于并行数据处理的装置，以及包括这种装置的相机系统
公开(公告)号：US07274390B2
公开(公告)日：2007-09-25
申请号：US10143646
申请日：2002-05-10
申请人： Leonardus Hendricus Maria Sevat , Cornelis Niessen
发明人： Leonardus Hendricus Maria Sevat , Cornelis Niessen
IPC分类号： H04N5/228 , G06F15/00
CPC分类号： H04N9/045 , G06F15/8023
摘要： The invention relates to a device for parallel processing data and to a camera system comprising such a device. The camera system (1) comprises a sensor matrix (2), a data converter (3), a DSP (4), a central controller (5), a data buffer (7) and a processor matrix (11) consisting of processors (12). The sensor matrix (2) converts incident electromagnetic radiation into pixel signals. The data converter (3) converts the pixel signals into data. The arrows (6) and (8) diagrammatically indicate the transport of pixel signals and data. The data buffer (7) is physically divided into a part (7A) and a part (7B) and functionally divided into an I/O register (9) and a memory bank (10). The central controller (5) co-ordinates the different tasks. The processors (12) and the data buffer (7) have data ports (13) and further data ports (14) with inputs and outputs which are mutually connected in an electrically conducting manner using the connections (15). The processors (12) are arranged in rows (16) which are mutually staggered, and columns (17). This makes all connections (15) substantially straight. Due to the amount of connections, this reduces the surface area.
摘要翻译：本发明涉及用于并行处理数据的装置和涉及包括这种装置的相机系统。相机系统（1）包括传感器矩阵（2），数据转换器（3），DSP（4），中央控制器（5），数据缓冲器（7）和处理器矩阵（11）（12）。传感器矩阵（2）将入射的电磁辐射转换为像素信号。数据转换器（3）将像素信号转换为数据。箭头（6）和（8）示意性地表示像素信号和数据的传输。数据缓冲器（7）被物理地划分为部分（7A）和部分（7B），并且功能上被划分为I / O寄存器（9）和存储体（10）。中央控制器（5）协调不同的任务。处理器（12）和数据缓冲器（7）具有数据端口（13）和具有输入和输出的另外的数据端口（14），所述输入和输出使用连接（15）以导电方式相互连接。处理器（12）被布置成彼此交错的行（16）和列（17）。这使得所有连接（15）基本上是直的。由于连接的数量，这减少了表面积。

3. 发明授权

US5276827A Data buffer for the duration of cyclically recurrent buffer periods 失效
标题翻译：数据缓冲区，持续周期性循环缓冲期
公开(公告)号：US5276827A
公开(公告)日：1994-01-04
申请号：US527997
申请日：1990-05-22
申请人： Antoine Delaruelle , Jozef L. Van Meerbergen , Cornelis Niessen , Owen P. McArdle
发明人： Antoine Delaruelle , Jozef L. Van Meerbergen , Cornelis Niessen , Owen P. McArdle
IPC分类号： G11B20/12 , G11B20/18 , H03M13/27 , H04B14/04 , G06F12/00 , G06F11/10 , H03M13/00
CPC分类号： G11B20/1809 , G11B2020/10666
摘要： A buffer memory device comprising memory locations for successively storing successive groups of data units, the successive groups being presented during successive phases, the data units in each group having different buffer periods which are recurrent for all groups. A modulo address generator generates, for each group of data units, a series of addresses for selected locations in a memory wherein the data units will be stored, there being logic address intervals between the successive addresses in the relevant series which correspond to the buffer periods of the respective data units. In every two successive series the memory addresses are shifted by one address interval unit with respect to each other. An efficient data occupation of the memory can thus be realized with simple addressing, since the write addresses during any phase can be used as the read addresses for already stored data units. The buffer device can be used as an interleaver or de interleaver for error correction in CD apparatus.
摘要翻译：一种缓冲存储器装置，包括用于连续地存储连续数据单元组的存储单元，连续组在连续阶段期间呈现，每组中的数据单元具有不同的缓冲周期，对于所有组来说都是复现的。模数地址发生器为每组数据单元生成存储器中所选位置的一系列地址，其中将存储数据单元，存在相应系列中相应于缓冲周期的连续地址之间的逻辑地址间隔的各个数据单元。在每两个连续的序列中，存储器地址相对于彼此移位一个地址间隔单元。因此，可以通过简单寻址来实现存储器的有效数据占用，因为在任何阶段期间的写入地址都可以用作已经存储的数据单元的读取地址。缓冲装置可以用作CD装置中的纠错的交织器或去交错器。

4. 发明授权

US5367638A Digital data processing circuit with control of data flow by control of the supply voltage 失效
标题翻译：数字数据处理电路通过控制电源电压控制数据流
公开(公告)号：US5367638A
公开(公告)日：1994-11-22
申请号：US951520
申请日：1992-09-25
申请人： Cornelis Niessen , Cornelis H. van Berkel
发明人： Cornelis Niessen , Cornelis H. van Berkel
IPC分类号： G06F1/26 , G06F1/32 , G06F5/06 , G06F13/38 , G06F13/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： Digital data processing electronic circuitry based on self-timed elements. The operating speed of the electronic circuitry is determined by its power supply voltage. Moreover, a buffer is connected either to the input or to the output of the electronic circuitry. A filling degree signal from the buffer is fed back to a control input of a power supply voltage controller for the electronic circuitry. In this way the supply voltage of the electronic circuitry is adjusted to control the data flow in such a way that the buffer tends not to fill up or to become empty.
摘要翻译：基于自定时元素的数字数据处理电子电路。电子电路的工作速度由其电源电压决定。此外，缓冲器连接到电子电路的输入端或输出端。来自缓冲器的填充度信号被反馈到用于电子电路的电源电压控制器的控制输入。以这种方式，调整电子电路的电源电压以控制数据流，使得缓冲器倾向于不填充或变空。

5. 发明授权

US4435806A Device for testing a circuit comprising sequential and combinatorial logic elements 失效
标题翻译：用于测试包括顺序和组合逻辑元件的电路的装置
公开(公告)号：US4435806A
公开(公告)日：1984-03-06
申请号：US282625
申请日：1981-07-13
申请人： Marinus T. M. Segers , Cornelis Niessen , Krijn Kuiper
发明人： Marinus T. M. Segers , Cornelis Niessen , Krijn Kuiper
IPC分类号： G01R31/28 , G01R31/3183 , G06F11/22 , G06F11/27
CPC分类号： G06F11/27
摘要： A device for processing digital signals includes combinatorial and sequential logic elements. For the testing of the device, a shift register can be formed from the sequential elements. A test pattern is applied thereto. The result of the processing of the test pattern is applied to the shift register. The output of the shift register is connected to a second shift register which forms a moving multibit sum pattern from a received series of result patterns by way of a feedback circuit to at least one Exclusive-OR-element. An output of the feedback circuit is connected to an input of the first shift register in order to apply a subsequent test pattern thereto. After completion of the test, the sum pattern formed is checked.
摘要翻译：用于处理数字信号的装置包括组合和顺序逻辑元件。对于器件的测试，可以从顺序元件形成移位寄存器。对其进行测试图案。将测试图案的处理结果应用于移位寄存器。移位寄存器的输出连接到第二移位寄存器，该第二移位寄存器通过反馈电路将所接收的一系列结果模式形成移动多位总和模式至至少一个异或元件。反馈电路的输出端连接到第一移位寄存器的输入端，以便对其进行随后的测试图案。测试完成后，检查形成的总和图案。

6. 发明授权

US4371795A Dynamic MOS-logic integrated circuit comprising a separate arrangement of combinatory and sequential logic elements 失效
标题翻译：动态MOS逻辑集成电路包括组合和顺序逻辑元件的单独排列
公开(公告)号：US4371795A
公开(公告)日：1983-02-01
申请号：US073571
申请日：1979-09-07
申请人： Cornelis Mulder , Leendert Nederlof , Cornelis Niessen , Rene M. G. Wijnhoven , Roelof H. W. Salters
发明人： Cornelis Mulder , Leendert Nederlof , Cornelis Niessen , Rene M. G. Wijnhoven , Roelof H. W. Salters
IPC分类号： H03K19/096 , H03K19/173 , H03K19/08 , H03K19/12
CPC分类号： H03K19/173 , H03K19/096
摘要： An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.
摘要翻译：动态MOS逻辑中的集成电路由组合和顺序逻辑元件组成。后者中的每一个包括一系列输入门，中间门和输出门，其被激活以由时钟脉冲周期的第一个和后续相的相应相位导通。组合逻辑元件都由单一类型的栅极组成，而输入信号通过顺序逻辑元件施加，输出信号经由后一个元件再次输出。因此，在组合网络中，唯一的干扰类型仍然是相关的。

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