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61. 发明授权

US06953728B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06953728B2
公开(公告)日：2005-10-11
申请号：US10775236
申请日：2004-02-11
申请人： Eiichi Murakami , Akio Nishida , Kazunori Umeda , Kousuke Okuyama , Toshiaki Yamanaka , Jiro Yugami , Shinichiro Kimura
发明人： Eiichi Murakami , Akio Nishida , Kazunori Umeda , Kousuke Okuyama , Toshiaki Yamanaka , Jiro Yugami , Shinichiro Kimura
IPC分类号： H01L29/43 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/331 , H01L21/8222
CPC分类号： H01L27/10894 , H01L21/823412 , H01L21/823462 , H01L27/105 , H01L27/10873
摘要： This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
摘要翻译：该半导体器件制造方法包括以下步骤：在衬底的第一区域形成厚栅氧化膜（厚氧化物膜），在第二区域形成薄的栅极氧化膜（薄氧化物层），然后施加氧氮化到这些栅氧化膜; 在这些栅极氧化膜上形成栅电极至1d; 以及在形成栅电极的步骤之前或之后，将含有氮或氮原子的离子注入到所述堰栅氧化膜（厚氧化物膜）和所述衬底之间的界面的至少一部分中，从而形成高度氧氮化地区。以这种方式，在并入具有薄栅极绝缘膜的MISFET和具有厚栅极绝缘膜的MISFET的半导体器件中，具有厚栅极绝缘膜的MISFET的热载流子可靠性得到改善。

62. 发明申请

US20050085039A1 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same 有权
标题翻译：具有锥形侧壁栅极的非易失性半导体存储器件及其制造方法
公开(公告)号：US20050085039A1
公开(公告)日：2005-04-21
申请号：US10901347
申请日：2004-07-29
申请人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4232 , H01L29/792
摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.
摘要翻译：在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

63. 发明申请

US20050035428A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20050035428A1
公开(公告)日：2005-02-17
申请号：US10946000
申请日：2004-09-22
申请人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/76
CPC分类号： H01L27/105 , H01L27/10897
摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.
摘要翻译：提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对用于构成读出放大器。假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差可以减少MISFET对。

64. 发明授权

US06791134B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06791134B2
公开(公告)日：2004-09-14
申请号：US10205421
申请日：2002-07-26
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小，随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触（33），外围电路区域和存储单元区域之间的台阶高度显着降低。

65. 发明授权

US06727146B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06727146B2
公开(公告)日：2004-04-27
申请号：US10288448
申请日：2002-11-06
申请人： Eiichi Murakami , Akio Nishida , Kazunori Umeda , Kousuke Okuyama , Toshiaki Yamanaka , Jiro Yugami , Shinichiro Kimura
发明人： Eiichi Murakami , Akio Nishida , Kazunori Umeda , Kousuke Okuyama , Toshiaki Yamanaka , Jiro Yugami , Shinichiro Kimura
IPC分类号： H01L218234
CPC分类号： H01L27/10894 , H01L21/823412 , H01L21/823462 , H01L27/105 , H01L27/10873
摘要： This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
摘要翻译：该半导体器件制造方法包括以下步骤：在衬底的第一区域形成厚栅氧化膜（厚氧化物膜），在第二区域形成薄的栅极氧化膜（薄氧化物层），然后施加氧氮化到这些栅氧化膜; 在这些栅极氧化膜上形成栅电极至1d; 以及在形成栅电极的步骤之前或之后，将含有氮或氮原子的离子注入到所述堰栅氧化膜（厚氧化物膜）和所述衬底之间的界面的至少一部分中，从而形成高度氧氮化地区。以这种方式，在并入具有薄栅极绝缘膜的MISFET和具有厚栅极绝缘膜的MISFET的半导体器件中，具有厚栅极绝缘膜的MISFET的热载流子可靠性得到改善。

66. 发明授权

US06677194B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06677194B2
公开(公告)日：2004-01-13
申请号：US10162573
申请日：2002-06-06
申请人： Toshiaki Yamanaka , Akio Nishida , Yasuko Yoshida , Shuji Ikeda , Kenichi Kuroda , Shiro Kamohara , Shinichiro Kimura , Eiichi Murakami , Hideyuki Matsuoka , Masataka Minami
发明人： Toshiaki Yamanaka , Akio Nishida , Yasuko Yoshida , Shuji Ikeda , Kenichi Kuroda , Shiro Kamohara , Shinichiro Kimura , Eiichi Murakami , Hideyuki Matsuoka , Masataka Minami
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/2652 , H01L21/823842 , H01L21/823892
摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.
摘要翻译：低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

67. 发明授权

US06538945B2 Sense amplifiers having reduced Vth deviation 有权
公开(公告)号：US06538945B2
公开(公告)日：2003-03-25
申请号：US10050561
申请日：2002-01-18
申请人： Riichiro Takemura , Tsugio Takahashi , Masayuki Nakamura , Ryo Nagai , Norikatsu Takaura , Tomonori Sekiguchi , Shinichiro Kimura
发明人： Riichiro Takemura , Tsugio Takahashi , Masayuki Nakamura , Ryo Nagai , Norikatsu Takaura , Tomonori Sekiguchi , Shinichiro Kimura
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C11/4091 , H01L21/823807 , H01L27/092 , H01L27/10873 , H01L27/10897
摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

68. 发明授权

US06204184B1 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06204184B1
公开(公告)日：2001-03-20
申请号：US09276969
申请日：1999-03-26
申请人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
发明人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
IPC分类号： H01L21302
CPC分类号： H01L27/10894 , H01L21/31053 , H01L21/76229 , H01L21/823437 , H01L21/823481 , H01L27/10814
摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, the insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.
摘要翻译：在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽场区域和半导体衬底。然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻将绝缘膜部分地从存储垫部分除去。在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

69. 发明授权

US08643117B2 Semiconductor device, method for manufacturing same, and semiconductor storage device 有权
标题翻译：半导体装置及其制造方法以及半导体存储装置
公开(公告)号：US08643117B2
公开(公告)日：2014-02-04
申请号：US13145108
申请日：2010-01-18
申请人： Ryuta Tsuchiya , Nobuyuki Sugii , Yusuke Morita , Hiroyuki Yoshimoto , Takashi Ishigaki , Shinichiro Kimura
发明人： Ryuta Tsuchiya , Nobuyuki Sugii , Yusuke Morita , Hiroyuki Yoshimoto , Takashi Ishigaki , Shinichiro Kimura
IPC分类号： H01L21/70
CPC分类号： H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/41783 , H01L29/665 , H01L29/78648
摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.
摘要翻译：在以高功率低功耗工作的SOI-MISFET中，元件面积减小。虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

70. 发明授权

US08409936B2 Method for manufacturing a semiconductor device by forming portions thereof at the same time 有权
标题翻译：通过同时形成半导体器件来制造半导体器件的方法
公开(公告)号：US08409936B2
公开(公告)日：2013-04-02
申请号：US13363268
申请日：2012-01-31
申请人： Ryuta Tsuchiya , Shinichiro Kimura
发明人： Ryuta Tsuchiya , Shinichiro Kimura
IPC分类号： H01L21/84
CPC分类号： H01L27/12 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1207
摘要： A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.
摘要翻译：一种器件及其制造方法，其中，器件包括单晶半导体衬底和通过薄的掩埋绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的SOI衬底以相同的步骤形成SOI型MISFET和体型MISFET的良好扩散层区域，漏极区域，栅极绝缘膜和栅极电极。本体型MISFET和SOI型MISFET形成在同一衬底上，从而通过制造SOI型MISFET和体型MISFET的制造步骤，可以减少电路板面积并简化工艺。

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