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1. 发明授权

US06204184B1 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06204184B1
公开(公告)日：2001-03-20
申请号：US09276969
申请日：1999-03-26
申请人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
发明人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
IPC分类号： H01L21302
CPC分类号： H01L27/10894 , H01L21/31053 , H01L21/76229 , H01L21/823437 , H01L21/823481 , H01L27/10814
摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, the insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.
摘要翻译：在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽场区域和半导体衬底。然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻将绝缘膜部分地从存储垫部分除去。在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

2. 发明授权

US06498100B2 Method of manufacturing semiconductor devices 有权
公开(公告)号：US06498100B2
公开(公告)日：2002-12-24
申请号：US09996918
申请日：2001-11-30
申请人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
发明人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
IPC分类号： H01L21302
CPC分类号： H01L27/10894 , H01L21/31053 , H01L21/76229 , H01L21/823437 , H01L21/823481 , H01L27/10814
摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

3. 发明授权

US06380085B2 Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06380085B2
公开(公告)日：2002-04-30
申请号：US09750061
申请日：2000-12-29
申请人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
发明人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
IPC分类号： H01L21302
CPC分类号： H01L27/10894 , H01L21/31053 , H01L21/76229 , H01L21/823437 , H01L21/823481 , H01L27/10814
摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.
摘要翻译：在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽场区域和半导体衬底。然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻部分地从存储垫部分去除绝缘膜。在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

4. 发明授权

US06657248B1 Semiconductor device having groove isolation structure and gate oxide films with different thickness 有权
标题翻译：具有沟槽隔离结构的半导体器件和不同厚度的栅极氧化膜
公开(公告)号：US06657248B1
公开(公告)日：2003-12-02
申请号：US09432460
申请日：1999-11-02
申请人： Nozomu Matsuzaki , Takashi Kobayashi , Hitoshi Kume , Toshiyuki Mine , Kikuo Kusukawa , Norio Suzuki , Kenji Takahashi , Toshiaki Nishimoto , Masataka Kato
发明人： Nozomu Matsuzaki , Takashi Kobayashi , Hitoshi Kume , Toshiyuki Mine , Kikuo Kusukawa , Norio Suzuki , Kenji Takahashi , Toshiaki Nishimoto , Masataka Kato
IPC分类号： H01L27108
CPC分类号： H01L27/105 , H01L27/10897
摘要： There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallow groove isolation structure. In the present invention, a bird's beak is disposed at the surface edge of a shallow isolation structure GROX11 just below gate electrode POLY11 and in contact with the gate insulation film HOX1 to form the gate insulation film HOX1 previously. This can ensure normal gate withstand voltage of the MOS transistor and favorable device isolation withstand voltage and increased integration degree simultaneously.
摘要翻译：存在栅极氧化膜的厚度增加以使栅极氧化膜的厚度急剧增加并且栅极氧化膜的厚度局部增加以降低浅沟槽隔离结构的表面边缘处的栅极耐受电压的问题。在本发明中，将鸟嘴设置在正好位于栅电极POLY11正下方的浅隔离结构GROX11的表面边缘处，并且与栅极绝缘膜HOX1接触以预先形成栅极绝缘膜HOX1。这可以确保MOS晶体管的正常栅极耐受电压，并且同时具有良好的器件隔离耐受电压和增加的积分度。

5. 发明授权

US07397104B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07397104B2
公开(公告)日：2008-07-08
申请号：US10778081
申请日：2004-02-17
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L21/00
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
摘要翻译：提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半。

6. 发明授权

US06720234B2 Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing 有权
标题翻译：半导体集成电路器件及其制造方法涉及使用圆形加工的浅槽隔离的缩小宽度
公开(公告)号：US06720234B2
公开(公告)日：2004-04-13
申请号：US10366423
申请日：2003-02-14
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要翻译：通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便具有凸形圆形的截面形状。

7. 发明授权

US06562695B1 Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing 有权
标题翻译：半导体集成电路器件及其制造方法涉及使用圆形加工的浅槽隔离的缩小宽度
公开(公告)号：US06562695B1
公开(公告)日：2003-05-13
申请号：US09889018
申请日：2001-07-10
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要翻译：通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便具有凸形圆形的截面形状。

8. 发明授权

US5619055A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5619055A
公开(公告)日：1997-04-08
申请号：US429882
申请日：1995-04-27
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加存储单元存储节点被实现，从而减少软错误的发生。通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

9. 发明授权

US5700705A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5700705A
公开(公告)日：1997-12-23
申请号：US470452
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元的制造，其中负载MISFET堆叠在半导体衬底上方和驱动MISFET上方。每个负载MISFET的制造包括在同一多晶硅膜内形成源极，漏极和沟道区域，以及由不同层导电膜（例如多晶膜）组成的栅电极，而不是驱动MISFET。具有这种堆叠布置的存储单元的制造有助于其每个负载MISFET的源极（漏极）区域和栅极电极的图案化，以使得彼此之间具有重叠关系，从而增加与每个负载MISFET相关联的有效电容存储单元存储节点。驱动和负载MISFET的栅电极分别由n型或n型和p型多晶硅膜形成，并且在第一和第二p沟道负载MISFET的漏极区之间形成电连接与第一和第二n沟道驱动MISFET的漏极区分别通过分离的多晶硅膜。此外，通过第一和第二驱动MISFET的多晶硅栅电极，在第一和第二负载MISFET的多晶硅栅电极与第二和第一驱动MISFET的漏极区域之间形成电连接此外，SRAM的存储单元分别。

10. 发明授权

US5194749A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5194749A
公开(公告)日：1993-03-16
申请号：US837689
申请日：1992-02-19
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.
摘要翻译：在CMOS型SRAM的存储单元中，具有作为源极，漏极和沟道区域的多晶硅膜的负载MISFET堆叠在驱动MISFET上，驱动MISFET和负载MISFET的栅电极由不同层中的导电膜构成。设置在多晶硅膜上的源极和漏极的面积与负载MISFET的栅电极重叠。

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