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1. 发明授权

US06677194B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06677194B2
公开(公告)日：2004-01-13
申请号：US10162573
申请日：2002-06-06
申请人： Toshiaki Yamanaka , Akio Nishida , Yasuko Yoshida , Shuji Ikeda , Kenichi Kuroda , Shiro Kamohara , Shinichiro Kimura , Eiichi Murakami , Hideyuki Matsuoka , Masataka Minami
发明人： Toshiaki Yamanaka , Akio Nishida , Yasuko Yoshida , Shuji Ikeda , Kenichi Kuroda , Shiro Kamohara , Shinichiro Kimura , Eiichi Murakami , Hideyuki Matsuoka , Masataka Minami
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/2652 , H01L21/823842 , H01L21/823892
摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.
摘要翻译：低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

2. 发明授权

US5880497A Semiconductor integrated circuit device having capacitance element and process of manufacturing the same 失效
标题翻译：具有电容元件的半导体集成电路器件及其制造方法
公开(公告)号：US5880497A
公开(公告)日：1999-03-09
申请号：US592235
申请日：1996-01-26
申请人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
发明人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
IPC分类号： H01L27/11
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
摘要翻译：其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

3. 发明授权

US5508540A Semiconductor integrated circuit device and process of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5508540A
公开(公告)日：1996-04-16
申请号：US190596
申请日：1994-02-02
申请人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
发明人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
IPC分类号： H01L27/11 , H01L27/108 , H01L29/04 , H01L29/76
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
摘要翻译：其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

4. 发明授权

US07893505B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07893505B2
公开(公告)日：2011-02-22
申请号：US12362995
申请日：2009-01-30
申请人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
发明人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译：为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。在布线上形成用作电容绝缘膜的氮化硅膜和上电极。电容可以由布线，氮化硅膜和上电极形成。

5. 发明申请

US20060128094A1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060128094A1
公开(公告)日：2006-06-15
申请号：US11342695
申请日：2006-01-31
申请人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
发明人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L21/8242
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译：为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。在布线上形成用作电容绝缘膜的氮化硅膜和上电极。电容可以由布线，氮化硅膜和上电极形成。

6. 发明授权

US07488639B2 Method of manufacturing a semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07488639B2
公开(公告)日：2009-02-10
申请号：US11342695
申请日：2006-01-31
申请人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
发明人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L21/8238
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译：为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。在布线上形成用作电容绝缘膜的氮化硅膜和上电极。电容可以由布线，氮化硅膜和上电极形成。

7. 发明授权

US07067864B2 SRAM having an improved capacitor 有权
标题翻译： SRAM具有改进的电容器
公开(公告)号：US07067864B2
公开(公告)日：2006-06-27
申请号：US10363055
申请日：2001-12-26
申请人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
发明人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L27/108
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译：为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。在布线上形成用作电容绝缘膜的氮化硅膜和上电极。电容可以由布线，氮化硅膜和上电极形成。

8. 发明申请

US20090218608A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20090218608A1
公开(公告)日：2009-09-03
申请号：US12362995
申请日：2009-01-30
申请人： Akio NISHIDA , Yasuko Yoshida , Shuji Ikeda
发明人： Akio NISHIDA , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译：为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。在布线上形成用作电容绝缘膜的氮化硅膜和上电极。电容可以由布线，氮化硅膜和上电极形成。

9. 发明申请

US20100044793A1 SEMICONDUCTOR DEVICE HAVING A PLURALITY OF MISFETS FORMED ON A MAIN SURFACE OF A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：在半导体基板的主表面上形成多个MISFET的半导体器件
公开(公告)号：US20100044793A1
公开(公告)日：2010-02-25
申请号：US12609323
申请日：2009-10-30
申请人： Yutaka Hoshino , Shuji Ikeda , Isao Yoshida , Shiro Kamohara , Megumi Kawakami , Tomoyuki Miyake , Masatoshi Morikawa
发明人： Yutaka Hoshino , Shuji Ikeda , Isao Yoshida , Shiro Kamohara , Megumi Kawakami , Tomoyuki Miyake , Masatoshi Morikawa
IPC分类号： H01L29/78
CPC分类号： H01L29/66659 , H01L21/823475 , H01L21/823871 , H01L23/4827 , H01L23/53219 , H01L23/53295 , H01L27/0255 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/4175 , H01L29/41758 , H01L29/42368 , H01L29/4238 , H01L29/4916 , H01L29/7835 , H01L29/861 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d(M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
摘要翻译：在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

10. 发明申请

US20050017296A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050017296A1
公开(公告)日：2005-01-27
申请号：US10921327
申请日：2004-08-19
申请人： Yutaka Hoshino , Shuji Ikeda , Isao Yoshida , Shiro Kamohara , Megumi Kawakami , Tomoyuki Miyake , Masatoshi Morikawa
发明人： Yutaka Hoshino , Shuji Ikeda , Isao Yoshida , Shiro Kamohara , Megumi Kawakami , Tomoyuki Miyake , Masatoshi Morikawa
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L23/482 , H01L23/532 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/80
CPC分类号： H01L29/66659 , H01L21/823475 , H01L21/823871 , H01L23/4827 , H01L23/53219 , H01L23/53295 , H01L27/0255 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/4175 , H01L29/41758 , H01L29/42368 , H01L29/4238 , H01L29/4916 , H01L29/7835 , H01L29/861 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
摘要翻译：在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

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