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61. 发明授权

US06654226B2 Thermal low k dielectrics 失效
标题翻译：热低k电介质
公开(公告)号：US06654226B2
公开(公告)日：2003-11-25
申请号：US10094520
申请日：2002-03-08
申请人： Charles E. May , Derryl D. J. Allman
发明人： Charles E. May , Derryl D. J. Allman
IPC分类号： H01G406
CPC分类号： H01L21/02129 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L21/31625 , H01L21/76828
摘要： An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.
摘要翻译：一种具有非绝缘材料的电绝缘层的集成电路，其中所述电绝缘层设置在至少两个导电元件之间。非导电材料选自具有在经受热处理时降低的k值的材料组。非导电材料最优选为硼硅氧烷。

62. 发明授权

US06387284B2 On-chip single layer horizontal deflecting waveguide and damascene method of fabricating the same 有权
标题翻译：片上单层水平偏转波导和镶嵌方法制作
公开(公告)号：US06387284B2
公开(公告)日：2002-05-14
申请号：US09876749
申请日：2001-06-06
申请人： Verne C. Hornbeck , Derryl D. J. Allman
发明人： Verne C. Hornbeck , Derryl D. J. Allman
IPC分类号： G02B610
CPC分类号： G02B6/136 , G02B6/125 , G02B6/132 , G02B2006/12104 , G02B2006/12119 , G02B2006/1215
摘要： A horizontal deflecting optical waveguide is formed in an integrated circuit-like structure having a substrate and at least one layer of dielectric material above the substrate. A trench is formed in the dielectric material, and the trench has first and second portions angularly joined at a bent portion. A reflective layer of material adjoins, conforms to and extends along the side walls of the trench. A core of optically transmissive material conforms to the reflective layer within the trench. The reflective layer forms a wall at the bent portion which reflects light from the core located in one portion into the core located in the other portion.
摘要翻译：水平偏转光波导形成为具有衬底和在衬底上方的至少一层电介质材料的集成电路状结构。在电介质材料中形成沟槽，并且沟槽具有在弯曲部分处成角度地接合的第一和第二部分。材料的反射层邻接，沿着沟槽的侧壁并沿其延伸。透光材料的核心符合沟槽内的反射层。反射层在弯曲部分处形成壁，其将来自位于一个部分中的芯的光反射到位于另一部分中的芯中。

63. 发明授权

US06354908B2 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system 有权
标题翻译：用共焦光学系统检测半导体晶片的平坦化外层的方法和装置
公开(公告)号：US06354908B2
公开(公告)日：2002-03-12
申请号：US09754429
申请日：2001-01-04
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12 , H01L21/67253
摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.
摘要翻译：利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。还公开了一种用于抛光半导体晶片的第一侧的装置。

64. 发明授权

US06341056B1 Capacitor with multiple-component dielectric and method of fabricating same 有权
标题翻译：具有多组分电介质的电容器及其制造方法
公开(公告)号：US06341056B1
公开(公告)日：2002-01-22
申请号：US09573123
申请日：2000-05-17
申请人： Derryl D. J. Allman , Brian Bystedt
发明人： Derryl D. J. Allman , Brian Bystedt
IPC分类号： H01G420
CPC分类号： H01G4/20
摘要： A capacitor has a pair of plates separated by a capacitor dielectric material which is formed of multiple separate layers of different dielectric materials having different electrical characteristics. The different electrical characteristics are represented by linearity curves that curve relatively oppositely with respect to one another. Combining the different dielectric materials and separate layers achieves selected electrical characteristics from the overall capacitor dielectric material. The capacitor dielectric material may be formed with a top layer, a middle layer and a bottom layer. The middle layer may be formed of relatively high leakage dielectric and/or relatively high dielectric constant material, and the top and bottom layers may be formed of barrier material which is substantially resistant to leakage current and which exhibits a relatively lower dielectric constant.
摘要翻译：电容器具有由电容器介电材料隔开的一对板，该电容器电介质材料由具有不同电特性的不同介电材料的多个分开的层形成。不同的电特性由相对于彼此相对相对地弯曲的线性曲线表示。组合不同的介电材料和分离的层可以实现来自整个电容器介电材料的选定的电特性。电容器电介质材料可以形成有顶层，中间层和底层。中间层可以由相对高的泄漏电介质和/或相对高的介电常数材料形成，并且顶层和底层可以由阻挡材料形成，其基本上抵抗漏电流并且具有相对较低的介电常数。

65. 发明授权

US06324313B1 On-chip multiple layer vertically transitioning optical waveguide and damascene method of fabricating the same 有权
标题翻译：片上多层垂直转换光波导及其镶嵌方法制作
公开(公告)号：US06324313B1
公开(公告)日：2001-11-27
申请号：US09217184
申请日：1998-12-21
申请人： Derryl D. J. Allman , Verne C. Hornbeck
发明人： Derryl D. J. Allman , Verne C. Hornbeck
IPC分类号： G02B612
CPC分类号： G02B6/125 , G02B6/12002 , G02B6/132 , G02B6/136 , G02B2006/12104 , G02B2006/12119
摘要： An optical waveguide extends vertically within the interior of an IC-like structure to route optical signals between horizontal waveguides in different layers of horizontal optical interconnects. A light reflecting structure is positioned at the intersection of the horizontal and vertical waveguides to reflect the light. Multiple horizontal waveguides may join the vertical waveguide at a common intersection, to form a beam splitter or a beam combiner. Optical signals from one horizontal waveguide are diverted within the IC-like structure into another horizontal or vertical waveguide. The waveguide is formed with a light reflective structure at an intersection of the horizontal and vertical waveguides, and the waveguide is completed using damascene fabrication techniques.
摘要翻译：光波导在IC状结构的内部垂直延伸，以在水平光学互连的不同层中的水平波导之间路由光信号。光反射结构位于水平和垂直波导的交点处以反射光。多个水平波导可以在公共交叉点处连接垂直波导，以形成分束器或光束组合器。来自一个水平波导的光信号在IC-类结构内被转移到另一个水平或垂直波导中。波导在水平和垂直波导的交叉点处形成有光反射结构，并且波导使用镶嵌制造技术完成。

66. 发明授权

US06316276B1 Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance 有权
标题翻译：平面化包括第一反射物质和第二反射物质的半导体晶片的装置和方法
公开(公告)号：US06316276B1
公开(公告)日：2001-11-13
申请号：US09213803
申请日：1998-12-17
申请人： John W. Gregory , Derryl D. J. Allman
发明人： John W. Gregory , Derryl D. J. Allman
IPC分类号： H01L2100
CPC分类号： B24B37/013 , B24B37/042 , B24B49/12 , H01L21/31053 , H01L21/76224 , H01L21/763
摘要： A method of planarizing a semiconductor that includes (i) a substrate material, (ii) a first reflective substance positioned on the substrate material, (iii) an intermediate material positioned on the first reflective substance, wherein a channel is defined in a structure which includes the substrate, the first reflective substance, and the intermediate material, and (iv) a second reflective substance positioned on the intermediate material and in the channel is disclosed. The method includes the steps of (i) directing light onto a first side of the semiconductor wafer, (ii) polishing the first side of the semiconductor wafer in order to remove matter therefrom and expose the first reflective substance, the matter including the second reflective substance and the intermediate material, (iii) detecting when light directed in the directing step is simultaneously reflected by (A) the first reflective substance positioned on the substrate, and (B) the second reflective substance positioned in the channel, and generating an endpoint detection signal in response thereto, and (iv) terminating the polishing step in response to generation of the endpoint detection signal. An associated apparatus is also disclosed.
摘要翻译：一种平面化半导体的方法，包括：（i）衬底材料，（ii）位于衬底材料上的第一反射物质，（iii）位于第一反射物质上的中间材料，其中通道被限定在包括基板，第一反射物质和中间材料，以及（iv）位于中间材料和通道中的第二反射物质。该方法包括以下步骤：（i）将光引导到半导体晶片的第一面上，（ii）抛光半导体晶片的第一侧以从其中除去物质并露出第一反射物质，该物质包括第二反射物质物质和中间材料，（iii）检测在引导步骤中引导的光是否同时被（A）位于基底上的第一反射物质反射，以及（B）位于通道中的第二反射物质，并产生端点检测信号，以及（iv）响应于端点检测信号的产生而终止抛光步骤。还公开了一种相关装置。

67. 发明授权

US06284586B1 Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking 有权
标题翻译：集成电路器件及其制造方法使用化学机械抛光以在掩模之后的两层中去除材料
公开(公告)号：US06284586B1
公开(公告)日：2001-09-04
申请号：US09431439
申请日：1999-11-01
申请人： John J. Seliskar , Derryl D. J. Allman , John W. Gregory , James P. Yakura , Dim Lee Kwong
发明人： John J. Seliskar , Derryl D. J. Allman , John W. Gregory , James P. Yakura , Dim Lee Kwong
IPC分类号： H01L27148
CPC分类号： H01L28/40 , H01L27/0688 , H01L29/42324
摘要： The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.
摘要翻译：本发明涉及半导体器件，优选电容器及其形成方法。该方法在制造过程中仅添加一个附加的掩模步骤，并且减少了与各种层的对准有关的问题。在底部电极上形成相对较厚的绝缘层。具有使用掩模在绝缘层中蚀刻以暴露底部电极的一部分的侧壁的开口。一旦去除了掩模，然后在包括侧壁的整个结构上依次沉积介电层和导电层。此后，使用化学机械抛光来去除导电层和电介质层的部分，使得保留的导电层和电介质层形成例如集成电路电容器的顶部电极和电介质层。因此，顶部电极设置在保留电介质层的中心区域之间以及保留在电介质层的外围区域之间。

68. 发明授权

US06208029B1 Integrated circuit device with reduced cross talk 失效
标题翻译：具有减少串扰的集成电路器件
公开(公告)号：US06208029B1
公开(公告)日：2001-03-27
申请号：US08829745
申请日：1997-03-31
申请人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
发明人： Derryl D. J. Allman , Kenneth P. Fuchs , Gayle W. Miller , Samuel C. Gioia
IPC分类号： H01L2348
CPC分类号： H01L23/3171 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.
摘要翻译：通过旋转在半导体芯片的钝化层上施加低电介质材料以填充可能存在于顶层金属线之间的间隙，从而最小化可能存在于这些线之间的串扰的可能性。

69. 发明授权

US6077783A Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer 失效
标题翻译：用于基于通过半导体晶片传导的热量来检测抛光端点的方法和装置
公开(公告)号：US6077783A
公开(公告)日：2000-06-20
申请号：US109335
申请日：1998-06-30
申请人： Derryl D. J. Allman , David W. Daniel , Michael F. Chisholm
发明人： Derryl D. J. Allman , David W. Daniel , Michael F. Chisholm
IPC分类号： B24B37/04 , B24B49/04 , B24B49/12 , H01L21/321 , H01L21/302
CPC分类号： H01L21/3212 , B24B37/042 , B24B49/04 , B24B49/12
摘要： A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.
摘要翻译：公开了将半导体晶片的第一层向下抛光至半导体晶片的第二层的方法。该方法的一个步骤包括将半导体晶片的背表面加热到第一温度水平，以使半导体晶片的前表面具有第二温度水平。该方法的另一步骤包括抛光半导体晶片，从而从半导体晶片去除第一层的材料。当第一层的材料被去除时，抛光步骤使得前表面的第二温度水平以第一速率改变。该方法还包括响应于在抛光步骤期间指示第二层被抛光的第二速率改变的正面的第二温度水平来停止抛光步骤的步骤。还公开了抛光系统，其基于通过半导体晶片传导的热量来检测半导体晶片的抛光端点。

70. 发明授权

US5576224A Method for manufacturing a monitor element 失效
标题翻译：监控元件制造方法
公开(公告)号：US5576224A
公开(公告)日：1996-11-19
申请号：US460287
申请日：1995-06-02
申请人： James P. Yakura , Richard K. Cole , Matthew S. Von Thun , Crystal J. Hass , Derryl D. J. Allman
发明人： James P. Yakura , Richard K. Cole , Matthew S. Von Thun , Crystal J. Hass , Derryl D. J. Allman
IPC分类号： H01L21/66 , G01K1/02 , G01K7/00 , H01L21/00 , H01L21/465
CPC分类号： H01L21/67248 , G01K1/024 , G01K7/00 , H01L21/67103
摘要： A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.
摘要翻译：用于感测关于诸如经历制造或其它工艺的硅晶片的对象的温度的数据的方法和结构涉及使用与被处理物体类似的材料和构造的监视元件。可以在监视元件的表面上形成诸如闭环或螺旋段的结构，当与包括初级线圈，电流源和感测的变压器结构处于操作关系时用作次级线圈设备。感测装置感测由监视器元件的存在引起的初级线圈中的电特性的变化，从而可以确定与监视元件相关的温度或其他期望数据，其与对象的可比数据基本相同正在处理。

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