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1. 发明授权

US6077783A Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer 失效
标题翻译：用于基于通过半导体晶片传导的热量来检测抛光端点的方法和装置
公开(公告)号：US6077783A
公开(公告)日：2000-06-20
申请号：US109335
申请日：1998-06-30
申请人： Derryl D. J. Allman , David W. Daniel , Michael F. Chisholm
发明人： Derryl D. J. Allman , David W. Daniel , Michael F. Chisholm
IPC分类号： B24B37/04 , B24B49/04 , B24B49/12 , H01L21/321 , H01L21/302
CPC分类号： H01L21/3212 , B24B37/042 , B24B49/04 , B24B49/12
摘要： A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.
摘要翻译：公开了将半导体晶片的第一层向下抛光至半导体晶片的第二层的方法。该方法的一个步骤包括将半导体晶片的背表面加热到第一温度水平，以使半导体晶片的前表面具有第二温度水平。该方法的另一步骤包括抛光半导体晶片，从而从半导体晶片去除第一层的材料。当第一层的材料被去除时，抛光步骤使得前表面的第二温度水平以第一速率改变。该方法还包括响应于在抛光步骤期间指示第二层被抛光的第二速率改变的正面的第二温度水平来停止抛光步骤的步骤。还公开了抛光系统，其基于通过半导体晶片传导的热量来检测半导体晶片的抛光端点。

2. 发明授权

US06201253B1 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system 有权
标题翻译：用共焦光学系统检测半导体晶片的平坦化外层的方法和装置
公开(公告)号：US06201253B1
公开(公告)日：2001-03-13
申请号：US09177335
申请日：1998-10-22
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： G01N2186
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12 , H01L21/67253
摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.
摘要翻译：利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。还公开了一种用于抛光半导体晶片的第一侧的装置。

3. 发明授权

US6121147A Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance 有权
标题翻译：检测包括金属报告物质的半导体晶片的抛光终点层的装置和方法
公开(公告)号：US6121147A
公开(公告)日：2000-09-19
申请号：US209704
申请日：1998-12-11
申请人： David W. Daniel , John W. Gregory , Derryl D. J. Allman
发明人： David W. Daniel , John W. Gregory , Derryl D. J. Allman
IPC分类号： B24B37/04 , B24B49/12 , B24B57/02 , H01L21/3105 , H01L21/00
CPC分类号： B24B37/04 , B24B49/12 , B24B57/02 , H01L21/31053
摘要： A method of planarizing a semiconductor wafer to a distance from a semiconductor substrate of the wafer is disclosed. The method includes the step of forming in the wafer a metallic reporting substance that is at the predetermined distance from the substrate of the wafer. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method further includes the step of utilizing an atomic absorption spectroscopic technique to detect the presence of the metallic reporting substance in the material removed from the wafer. Moreover, the method includes the step of terminating the polishing step in response to the detection of the metallic reporting substance. An associated apparatus for polishing a semiconductor wafer down to a metallic reporting substance of the wafer is also described.
摘要翻译：公开了一种将半导体晶片平面化到与晶片的半导体衬底一段距离的方法。该方法包括在晶片上形成距晶片基板预定距离的金属报告物质的步骤。该方法还包括抛光晶片的第一侧以从晶片去除材料的步骤。该方法还包括利用原子吸收光谱技术来检测从晶片去除的材料中金属报告物质的存在的步骤。此外，该方法包括响应于金属报告物质的检测终止抛光步骤的步骤。还描述了用于将半导体晶片抛光到晶片的金属报告物质的相关设备。

4. 发明授权

US06354908B2 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system 有权
标题翻译：用共焦光学系统检测半导体晶片的平坦化外层的方法和装置
公开(公告)号：US06354908B2
公开(公告)日：2002-03-12
申请号：US09754429
申请日：2001-01-04
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12 , H01L21/67253
摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.
摘要翻译：利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。还公开了一种用于抛光半导体晶片的第一侧的装置。

5. 发明授权

US06241847B1 Method and apparatus for detecting a polishing endpoint based upon infrared signals 失效
标题翻译：用于基于红外信号检测抛光端点的方法和装置
公开(公告)号：US06241847B1
公开(公告)日：2001-06-05
申请号：US09107342
申请日：1998-06-30
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： H01L21301
CPC分类号： B24B37/013 , B24B37/042 , B24B49/04 , B24B49/12 , H01L21/3212
摘要： A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes polishing the first layer of the semiconductor wafer with a polishing surface having a chemical slurry positioned thereon. The polishing step causes an infrared spectrum to be emitted through the semiconductor wafer. Another step of the method includes detecting a rate of change of intensity level of the infrared spectrum and generating a control signal in response thereto. The method also includes halting the polishing step in response to generation of the control signal. Polishing systems are also disclosed which determine a polishing endpoint for a semiconductor wafer based upon an infrared spectrum generated due to a chemical slurry reacting with the semiconductor wafer.
摘要翻译：公开了将半导体晶片的第一层向下抛光至半导体晶片的第二层的方法。该方法的一个步骤包括用其上定位有化学浆料的抛光表面抛光半导体晶片的第一层。抛光步骤使红外光谱通过半导体晶片发射。该方法的另一步骤包括检测红外光谱的强度水平的变化率并响应于此产生控制信号。该方法还包括响应于控制信号的产生停止抛光步骤。还公开了抛光系统，其基于由于与半导体晶片的化学浆料反应而产生的红外光谱确定半导体晶片的抛光端点。

6. 发明授权

US06235590B1 Fabrication of differential gate oxide thicknesses on a single integrated circuit chip 有权
标题翻译：在单个集成电路芯片上制造差分栅极氧化物厚度
公开(公告)号：US06235590B1
公开(公告)日：2001-05-22
申请号：US09216394
申请日：1998-12-18
申请人： David W. Daniel , Dianne G. Pinello , Michael F. Chisholm
发明人： David W. Daniel , Dianne G. Pinello , Michael F. Chisholm
IPC分类号： H01L218234
CPC分类号： H01L21/8234 , H01L21/823462
摘要： Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides. The oxynitride gates can have a nitrogen content in a range of about 0.2 to about 2.0 percent which can prevent the diffusion of boron ions from the gate electrodes into the oxynitride gates, thereby improving device characteristics. The oxynitride gates of different thicknesses are suitable for high and low voltage devices on the same integrated circuit.
摘要翻译：用于制造具有栅极氧化物具有不同厚度和高氮含量的器件的集成电路的技术包括在含氮气体的环境中形成至少高达2.0个大气压的栅极氧化物。在一个实施方式中，衬底包括用于形成具有第一厚度的栅极氧化物的第一器件的第一区域和用于形成具有第二不同厚度的栅极氧化物的第二器件的第二区域。第一氧氮化物层在包含含氮气体的环境中在约10至约15个大气压的压力下在第一和第二区域上形成。去除第一氧氮化物层的一部分以暴露第二区域上的衬底的表面。随后，在约10至约15个大气压的压力下，在包含含氮气体的环境中的第一和第二区域上形成第二氮氧化物以形成第一和第二栅极氧化物。在第一和第二栅极氧化物上形成各自的栅电极。氧氮化物栅极可以具有在约0.2至约2.0％的范围内的氮含量，这可以防止硼离子从栅电极扩散到氮氧化物栅极中，从而提高器件特性。不同厚度的氮氧化物栅极适用于同一集成电路上的高电压和低电压器件。

7. 发明授权

US6069048A Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits 有权
标题翻译：由于CMOS和其他集成电路中的种植体而导致硅缺陷引起的故障的减少
公开(公告)号：US6069048A
公开(公告)日：2000-05-30
申请号：US163623
申请日：1998-09-30
申请人： David W. Daniel
发明人： David W. Daniel
IPC分类号： H01L21/265 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/8238 , H01L12/331
CPC分类号： H01L21/266 , H01L21/2652 , H01L21/324 , H01L21/76218 , H01L21/8238
摘要： A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of the integrated circuit. The buried layer implant is the final implanting step during fabrication of the integrated circuit structure. In another technique, fabricating the integrated circuit structure includes performing multiple sequential processes some of which are performed at elevated temperatures above about 500.degree. C. A buried layer is implanted beneath a surface of the integrated circuit. After implanting the buried layer, the substrate is subjected to a fabrication process at an elevated temperature above about 800.degree. C. only once. Propagation of defects, such as in-the-range defects or ion enhanced stacking faults, from the buried layer to other device layers during the fabrication process is reduced.
摘要翻译：在CMOS或其他集成电路结构中减少硅缺陷引起的晶体管故障（例如闩锁）的技术包括在衬底上制造集成电路结构并且在集成电路的表面下方埋入掩埋层。埋层植入是在集成电路结构的制造期间的最终植入步骤。在另一种技术中，制造集成电路结构包括执行多个顺序处理，其中一些在高于约500℃的高温下进行。在集成电路的表面下方埋设掩埋层。在埋入掩埋层之后，将衬底在高于约800℃的高温下仅进行一次制造工艺。减少了在制造过程中从掩埋层到其它器件层的缺陷的传播，例如范围内缺陷或离子增强堆垛层错。

8. 发明授权

US5858828A Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor 失效
标题翻译：使用MEV注入在NPN双极晶体管中形成垂直调制的N +掩埋层
公开(公告)号：US5858828A
公开(公告)日：1999-01-12
申请号：US801668
申请日：1997-02-18
申请人： John J. Seliskar , David W. Daniel , Todd A. Randazzo
发明人： John J. Seliskar , David W. Daniel , Todd A. Randazzo
IPC分类号： H01L21/266 , H01L21/331 , H01L21/74 , H01L29/08 , H01L21/22 , H01L21/265 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/266 , H01L21/74 , H01L29/0821 , Y10S438/95
摘要： High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.
摘要翻译：使用通过改变一个或多个膜的垂直厚度的高能量注入来形成垂直调制的子集电极，其同时降低垂直集成的双极器件中的寄生集电极电阻的垂直和侧向分量。避免了沉降式植入物的需要或其他附加步骤以减少集电极电阻。必要的处理修改可以容易地集成到传统的双极或BiCMOS工艺流程中。

9. 发明授权

US07095483B2 Process independent alignment marks 有权
标题翻译：过程独立对齐标记
公开(公告)号：US07095483B2
公开(公告)日：2006-08-22
申请号：US11000772
申请日：2004-12-01
申请人： David W. Daniel , James R. B. Elmer
发明人： David W. Daniel , James R. B. Elmer
IPC分类号： G03B27/42 , G03B27/58 , G03B27/62 , G01B11/00 , G03B27/54
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002 , H01L2924/09701 , Y10S438/975 , H01L2924/00
摘要： An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate further has at least one alignment mark on the second surface. A mask support supports the mask in proximity to the first surface of the substrate. A substrate support supports the substrate with the first surface in proximity to the mask. An alignment means aligns the at least one alignment mark on the second surface of the substrate to the at least one complimentary alignment mark on the mask. An exposure source projects the image of the mask onto the first surface of the substrate, and a controller controls the mask support, substrate support, alignment means, and exposure source.
摘要翻译：一种用于将具有图像和至少一个互补对准标记的掩模对准到具有第一表面和基本上相对的第二表面的基板的设备。基板还在第二表面上具有至少一个对准标记。掩模支撑件支撑靠近基板的第一表面的掩模。衬底支撑件支撑具有靠近掩模的第一表面的衬底。对准装置将衬底的第二表面上的至少一个对准标记对准掩模上的至少一个互补对准标记。曝光源将掩模的图像投影到基板的第一表面上，并且控制器控制掩模支撑件，基板支撑件，对准装置和曝光源。

10. 发明授权

US6096625A Method for improved gate oxide integrity on bulk silicon 失效
标题翻译：在体硅上提高栅极氧化物完整性的方法
公开(公告)号：US6096625A
公开(公告)日：2000-08-01
申请号：US954006
申请日：1997-10-20
申请人： David W. Daniel , Theodore C. Moore , Crystal J. Hass
发明人： David W. Daniel , Theodore C. Moore , Crystal J. Hass
IPC分类号： H01L21/322
CPC分类号： H01L21/3225
摘要： The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.
摘要翻译：本发明提供一种在基板上制造半导体器件的方法。该方法包括通过加热来剥离基底以在基底内产生剥离区域。在将离子注入衬底之前形成屏幕氧化物层。在注入步骤期间保留该氧化物层。当形成半导体器件的栅极时，屏蔽氧化物层被去除。

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