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1. 发明授权

US06354908B2 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system 有权
标题翻译：用共焦光学系统检测半导体晶片的平坦化外层的方法和装置
公开(公告)号：US06354908B2
公开(公告)日：2002-03-12
申请号：US09754429
申请日：2001-01-04
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12 , H01L21/67253
摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.
摘要翻译：利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。还公开了一种用于抛光半导体晶片的第一侧的装置。

2. 发明授权

US06316276B1 Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance 有权
标题翻译：平面化包括第一反射物质和第二反射物质的半导体晶片的装置和方法
公开(公告)号：US06316276B1
公开(公告)日：2001-11-13
申请号：US09213803
申请日：1998-12-17
申请人： John W. Gregory , Derryl D. J. Allman
发明人： John W. Gregory , Derryl D. J. Allman
IPC分类号： H01L2100
CPC分类号： B24B37/013 , B24B37/042 , B24B49/12 , H01L21/31053 , H01L21/76224 , H01L21/763
摘要： A method of planarizing a semiconductor that includes (i) a substrate material, (ii) a first reflective substance positioned on the substrate material, (iii) an intermediate material positioned on the first reflective substance, wherein a channel is defined in a structure which includes the substrate, the first reflective substance, and the intermediate material, and (iv) a second reflective substance positioned on the intermediate material and in the channel is disclosed. The method includes the steps of (i) directing light onto a first side of the semiconductor wafer, (ii) polishing the first side of the semiconductor wafer in order to remove matter therefrom and expose the first reflective substance, the matter including the second reflective substance and the intermediate material, (iii) detecting when light directed in the directing step is simultaneously reflected by (A) the first reflective substance positioned on the substrate, and (B) the second reflective substance positioned in the channel, and generating an endpoint detection signal in response thereto, and (iv) terminating the polishing step in response to generation of the endpoint detection signal. An associated apparatus is also disclosed.
摘要翻译：一种平面化半导体的方法，包括：（i）衬底材料，（ii）位于衬底材料上的第一反射物质，（iii）位于第一反射物质上的中间材料，其中通道被限定在包括基板，第一反射物质和中间材料，以及（iv）位于中间材料和通道中的第二反射物质。该方法包括以下步骤：（i）将光引导到半导体晶片的第一面上，（ii）抛光半导体晶片的第一侧以从其中除去物质并露出第一反射物质，该物质包括第二反射物质物质和中间材料，（iii）检测在引导步骤中引导的光是否同时被（A）位于基底上的第一反射物质反射，以及（B）位于通道中的第二反射物质，并产生端点检测信号，以及（iv）响应于端点检测信号的产生而终止抛光步骤。还公开了一种相关装置。

3. 发明授权

US06284586B1 Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking 有权
标题翻译：集成电路器件及其制造方法使用化学机械抛光以在掩模之后的两层中去除材料
公开(公告)号：US06284586B1
公开(公告)日：2001-09-04
申请号：US09431439
申请日：1999-11-01
申请人： John J. Seliskar , Derryl D. J. Allman , John W. Gregory , James P. Yakura , Dim Lee Kwong
发明人： John J. Seliskar , Derryl D. J. Allman , John W. Gregory , James P. Yakura , Dim Lee Kwong
IPC分类号： H01L27148
CPC分类号： H01L28/40 , H01L27/0688 , H01L29/42324
摘要： The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.
摘要翻译：本发明涉及半导体器件，优选电容器及其形成方法。该方法在制造过程中仅添加一个附加的掩模步骤，并且减少了与各种层的对准有关的问题。在底部电极上形成相对较厚的绝缘层。具有使用掩模在绝缘层中蚀刻以暴露底部电极的一部分的侧壁的开口。一旦去除了掩模，然后在包括侧壁的整个结构上依次沉积介电层和导电层。此后，使用化学机械抛光来去除导电层和电介质层的部分，使得保留的导电层和电介质层形成例如集成电路电容器的顶部电极和电介质层。因此，顶部电极设置在保留电介质层的中心区域之间以及保留在电介质层的外围区域之间。

4. 发明授权

US5523964A Ferroelectric non-volatile memory unit 失效
标题翻译：铁电非易失性存储单元
公开(公告)号：US5523964A
公开(公告)日：1996-06-04
申请号：US224241
申请日：1994-04-07
申请人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , G11C11/223
摘要： An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf
摘要翻译：集成电路非易失性非破坏性读出存储单元包括具有第一和第二电极的铁电电容器，电容Cf和区域Af，以及具有形成栅极电容器的栅极，源极和漏极的晶体管具有面积Ag和栅极电容Cg，栅极重叠b和沟道深度a，其中电容器第一电极连接到晶体管的栅极。铁电材料具有介电常数εf，栅极绝缘体具有介电常数εg。恒定参考电压的源可连接到第一电极。位线连接到第二电极。在一个实施例中，第一电极和栅极是相同的导电构件。在另一个实施例中，第二电极和栅极是相同的导电构件，并且第一电极由晶体管源的延伸和栅极下方的漏极形成，铁电材料在源极和漏极延伸部分之间以及栅极之间。存储器单元具有参数关系：Cf <5xCg，Af / = 2a和epsilon g> / = epsilon f / 8。

5. 发明授权

US06201253B1 Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system 有权
标题翻译：用共焦光学系统检测半导体晶片的平坦化外层的方法和装置
公开(公告)号：US06201253B1
公开(公告)日：2001-03-13
申请号：US09177335
申请日：1998-10-22
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： G01N2186
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12 , H01L21/67253
摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.
摘要翻译：利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。还公开了一种用于抛光半导体晶片的第一侧的装置。

6. 发明授权

US5559733A Memory with ferroelectric capacitor connectable to transistor gate 失效
标题翻译：具有可连接到晶体管栅极的铁电电容器的存储器
公开(公告)号：US5559733A
公开(公告)日：1996-09-24
申请号：US482765
申请日：1995-06-07
申请人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
发明人： Larry D. McMillan , Takashi Mihara , Hiroyuki Yoshimori , John W. Gregory , Carlos A. Paz de Araujo
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , G11C11/223
摘要： A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.
摘要翻译：铁电存储器包括恒压源，具有第一和第二电极的电容器和具有栅极的晶体管。开关将晶体管的栅极交替地连接到第一电极和恒定电压源。在另一实施例中，存在两个铁电晶体管，并且每个电容器的第一电极都连接到晶体管的栅极和存储器外部的电压源。

7. 发明授权

US06541383B1 Apparatus and method for planarizing the surface of a semiconductor wafer 有权
标题翻译：用于平坦化半导体晶片表面的装置和方法
公开(公告)号：US06541383B1
公开(公告)日：2003-04-01
申请号：US09607169
申请日：2000-06-29
申请人： Derryl D. J. Allman , John W. Gregory
发明人： Derryl D. J. Allman , John W. Gregory
IPC分类号： H01L21302
CPC分类号： B24B53/017 , B24B37/042 , H01L21/31053 , H01L21/3212
摘要： An arrangement for planarizing a surface of a semiconductor wafer. The arrangement includes a planarizing member having a planarizing surface configured to be (i) positioned in contact with and (ii) moved relative to the surface of the semiconductor wafer so as to remove material from the surface of the semiconductor wafer such that the surface of the semiconductor wafer is planarized. The arrangement also includes an adherence promoting ligand chemically bonded to the planarizing surface of the planarizing member. The arrangement further includes an abrasion particle chemically bonded to the adherence promoting ligand such that the abrasion particle is attached to the planarizing surface of the planarizing member. The arrangement also includes a conditioning bar having a conditioning portion positioned in contact with a wafer track defined on the planarizing member. The conditioning portion is configured so that the conditioning portion extends completely across the wafer track. The arrangement still further includes a wafer carrier which (i) urges the surface of the semiconductor wafer against the planarizing surface at a first pressure for a first period of time and (ii) urges the surface of the semiconductor wafer against the planarizing surface at a second pressure for a second period of time. The first pressure is greater than the second pressure such that slurry is advanced from an outer periphery of the semiconductor wafer toward a center portion of the semiconductor wafer. An associated method of planarizing a surface of a semiconductor wafer is also disclosed.
摘要翻译：用于平坦化半导体晶片的表面的布置。该布置包括具有平坦化表面的平坦化构件，该平坦化构件被配置成（i）定位成与半导体晶片的表面接触和（ii）移动，以便从半导体晶片的表面去除材料，半导体晶片被平坦化。该布置还包括与平坦化构件的平坦化表面化学键合的粘附促进配体。该布置还包括与粘附促进配体化学结合的磨损颗粒，使得磨损颗粒附着到平坦化构件的平坦化表面。该布置还包括调节杆，其具有定位成与平坦化构件上限定的晶片轨道接触的调节部分。调理部分被配置成使得调理部分完全延伸穿过晶片轨道。该装置还包括晶片载体，其（i）在第一时间段内以第一压力将半导体晶片的表面压在平坦化表面上，并且（ii）在半导体晶片的表面上以一个第二次压力第二次。第一压力大于第二压力，使得浆料从半导体晶片的外周朝向半导体晶片的中心部分前进。还公开了一种使半导体晶片的表面平坦化的相关方法。

8. 发明授权

US06241847B1 Method and apparatus for detecting a polishing endpoint based upon infrared signals 失效
标题翻译：用于基于红外信号检测抛光端点的方法和装置
公开(公告)号：US06241847B1
公开(公告)日：2001-06-05
申请号：US09107342
申请日：1998-06-30
申请人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
发明人： Derryl D. J. Allman , David W. Daniel , John W. Gregory
IPC分类号： H01L21301
CPC分类号： B24B37/013 , B24B37/042 , B24B49/04 , B24B49/12 , H01L21/3212
摘要： A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes polishing the first layer of the semiconductor wafer with a polishing surface having a chemical slurry positioned thereon. The polishing step causes an infrared spectrum to be emitted through the semiconductor wafer. Another step of the method includes detecting a rate of change of intensity level of the infrared spectrum and generating a control signal in response thereto. The method also includes halting the polishing step in response to generation of the control signal. Polishing systems are also disclosed which determine a polishing endpoint for a semiconductor wafer based upon an infrared spectrum generated due to a chemical slurry reacting with the semiconductor wafer.
摘要翻译：公开了将半导体晶片的第一层向下抛光至半导体晶片的第二层的方法。该方法的一个步骤包括用其上定位有化学浆料的抛光表面抛光半导体晶片的第一层。抛光步骤使红外光谱通过半导体晶片发射。该方法的另一步骤包括检测红外光谱的强度水平的变化率并响应于此产生控制信号。该方法还包括响应于控制信号的产生停止抛光步骤。还公开了抛光系统，其基于由于与半导体晶片的化学浆料反应而产生的红外光谱确定半导体晶片的抛光端点。

9. 发明授权

US6115233A Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region 失效
标题翻译：集成电路器件具有电介质周边区域大于介电中心区域的电容器
公开(公告)号：US6115233A
公开(公告)日：2000-09-05
申请号：US673655
申请日：1996-06-28
申请人： John J. Seliskar , Derryl D. J. Allman , John W. Gregory , James P. Yakura , Dim Lee Kwong
发明人： John J. Seliskar , Derryl D. J. Allman , John W. Gregory , James P. Yakura , Dim Lee Kwong
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/423 , H01G4/005 , H01G4/228
CPC分类号： H01L28/40 , H01L27/0688 , H01L29/42324
摘要： The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.
摘要翻译：本发明涉及半导体器件，优选电容器及其形成方法。该方法在制造过程中仅增加了一个额外的掩蔽步骤，并且减少了与各种层的对准有关的问题。在底部电极上形成相对较厚的绝缘层。具有使用掩模在绝缘层中蚀刻以暴露底部电极的一部分的侧壁的开口。一旦去除了掩模，然后在包括侧壁的整个结构上依次沉积介电层和导电层。此后，使用化学机械抛光来去除导电层和电介质层的部分，使得保留的导电层和电介质层形成例如集成电路电容器的顶部电极和电介质层。因此，顶部电极设置在保留电介质层的中心区域之间以及保留在电介质层的外围区域之间。

10. 发明授权

US5868608A Subsonic to supersonic and ultrasonic conditioning of a polishing pad in a chemical mechanical polishing apparatus 失效
标题翻译：在化学机械抛光装置中对抛光垫进行超音速和超声波调理
公开(公告)号：US5868608A
公开(公告)日：1999-02-09
申请号：US696445
申请日：1996-08-13
申请人： Derryl D.J. Allman , John W. Gregory
发明人： Derryl D.J. Allman , John W. Gregory
IPC分类号： B24B1/04 , B24B53/007 , B24B53/017 , B24C5/00 , B24B55/00
CPC分类号： B24B53/017 , B24B1/04 , Y10S451/91
摘要： The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.
摘要翻译：本发明提供了一种用于调节抛光垫的方法和装置，其中浆料在抛光垫处被压力地定向。此外，能量（即，超声能量）可以被引入抛光垫而被添加到浆料中，其中抛光垫中的嵌入材料被去除或移动。

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