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51. 发明申请

US20060119402A1 Multi-frequency clock synthesizer 有权
标题翻译：多频时钟合成器
公开(公告)号：US20060119402A1
公开(公告)日：2006-06-08
申请号：US11270954
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell Hein , Michael Petrowski
发明人： Axel Thomsen , Yunteng Huang , Jerrell Hein , Michael Petrowski
IPC分类号： H03B21/00
CPC分类号： H03L7/23 , H03L7/0898 , H03L7/197 , H03L7/1976
摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.
摘要翻译：锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比反馈分频电路。频率选择机构选择多个存储值中的一个。选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

52. 发明授权

US07015733B2 Spread-spectrum clock generator using processing in the bitstream domain 失效
标题翻译：扩频时钟发生器利用比特流域中的处理
公开(公告)号：US07015733B2
公开(公告)日：2006-03-21
申请号：US10682839
申请日：2003-10-10
申请人： Horia Giuroiu
发明人： Horia Giuroiu
IPC分类号： H03L7/06
CPC分类号： H03L7/197 , H03L7/1976
摘要： A spread-spectrum phase-locked loop clock generator includes a PLL circuit, a modulation generator, a bit stream processor and a multiplexer. The modulation generator outputs a bitstream in response to an input signal and a control signal. The bitstream processor generates bitstream signals. The multiplexer outputs one of the bitstream signals in response to a frequency deviation control signal. The PLL circuit is controlled by the output of the multiplexer.
摘要翻译：扩频锁相环时钟发生器包括PLL电路，调制发生器，比特流处理器和多路复用器。调制发生器响应于输入信号和控制信号输出比特流。比特流处理器产生比特流信号。复用器响应于频率偏差控制信号而输出一个比特流信号。 PLL电路由多路复用器的输出控制。

53. 发明授权

US06980581B1 Adaptive spread spectrum 有权
标题翻译：自适应扩频
公开(公告)号：US06980581B1
公开(公告)日：2005-12-27
申请号：US09618622
申请日：2000-07-18
申请人： I-Teh Sha , Kuang-Yu Chen , Albert Chen
发明人： I-Teh Sha , Kuang-Yu Chen , Albert Chen
IPC分类号： G06F1/08 , H03L7/089 , H03L7/093 , H03L7/099 , H03L7/197 , H04B15/00 , H04K1/00 , H04L27/00 , H04L27/30
CPC分类号： H03L7/197 , G06F1/08 , H03L7/0898 , H03L7/093 , H03L7/099 , H04L27/0014
摘要： An apparatus comprising a circuit configured to generate a spread spectrum clock signal. The circuit may comprise a voltage controlled oscillator with a gain that may be automatically controlled.
摘要翻译：一种装置，包括被配置为产生扩频时钟信号的电路。电路可以包括具有可以被自动控制的增益的压控振荡器。

54. 发明申请

US20050281367A1 Clock synchroniser 有权
标题翻译：时钟同步器
公开(公告)号：US20050281367A1
公开(公告)日：2005-12-22
申请号：US10986994
申请日：2004-11-15
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03D3/18 , H03L7/08 , H03L7/087 , H03L7/18 , H03L7/197 , H04L7/00 , H04L7/02
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchroniser, for generating a local clock signal synchronised to a received clock signal, is described and claimed, along with a corresponding clock synchronisation method. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.
摘要翻译：用于产生与所接收的时钟信号同步的本地时钟信号的时钟同步器与相应的时钟同步方法一起被描述和要求保护。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和远程时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。优选地，时钟比较电路比较本地和接收的时钟信号的周期。

55. 发明授权

US06970701B1 Radio calibration by correcting the crystal frequency 有权
标题翻译：通过校正晶体频率进行无线电校准
公开(公告)号：US06970701B1
公开(公告)日：2005-11-29
申请号：US09702691
申请日：2000-11-01
申请人： Seste Dell'Aera
发明人： Seste Dell'Aera
IPC分类号： H03L7/16 , H03L7/197 , H04Q7/20
CPC分类号： H03L7/16 , H03J2200/07 , H03L7/197 , H03L7/1976
摘要： The present invention provides a simple and inexpensive method of calibrating radios. The present invention automatically corrects for crystal frequency drift by determining the true crystal frequency. Once the true crystal frequency has been measured and calculated, the proper multiplier required to produce a desired frequency can easily be found and implemented. The present invention allows for a constantly changing desired frequency without recalibration and without readjusting the crystal frequency once the true crystal frequency is known. Once the true crystal frequency is found, a proper multiplier can be calculated to produce the desired frequency. Continuously adjusting the multiplier thus allows for a changing desired frequency, thereby facilitating clear communications between radios, regardless of whether they are in motion or not.
摘要翻译：本发明提供了一种简单且廉价的无线电校准方法。本发明通过确定真实的晶体频率来自动校正晶体频率漂移。一旦已经测量和计算了真实的晶体频率，就可以很容易地发现和实现产生所需频率所需的适当乘法器。本发明允许恒定变化的期望频率，而不需要重新校准，一旦知道真实的晶体频率，就不需要重新调整晶体频率。一旦找到了真正的晶体频率，就可以计算一个合适的乘数来产生所需的频率。因此，连续调节乘法器可以实现所需的频率变化，从而便于无线电之间的清晰通信，无论它们是否在运动中。

56. 发明申请

US20050220240A1 Clock synchroniser and clock and data recovery apparatus and method 审中-公开
标题翻译：时钟同步器和时钟与数据恢复装置及方法
公开(公告)号：US20050220240A1
公开(公告)日：2005-10-06
申请号：US10900347
申请日：2004-07-28
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： G06F5/06 , G06F5/12 , H03L7/10 , H03L7/197 , H04J3/06 , H04L7/00 , H04L7/033 , H04L25/05
CPC分类号： H03L7/197 , G06F5/06 , G06F5/12 , G06F2205/061 , H03L7/10 , H04J3/0632
摘要： A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.
摘要翻译：时钟同步器以及并入时钟同步器的时钟和数据恢复装置与对应的时钟同步方法一起被描述。时钟同步器包含弹性缓冲器。接收到的时钟信号用于将数据进入缓冲器，本地生成的时钟用于将数据从缓冲器中提取出来。使用PLL合成本地时钟，并且使用来自弹性缓冲器的填充级信号来控制本地时钟频率，以保持缓冲器中期望的平均数据量，从而实现接收和本地时钟的同步。在优选实施例中，填充电平信号用于控制PLL的反馈路径中的可变分频器，其被提供有高度稳定的参考信号。因此产生了同步和低抖动的本地时钟。优选地，弹性缓冲器使用具有相对宽的字宽的计数器，并且由字的几个最低有效位提供了大大减少的深度，读和写指针的存储阵列。

57. 发明申请

US20050212793A1 Control unit and method for reducing interference patterns in the display of an image on a screen 有权
标题翻译：用于减少屏幕上图像显示中的干扰图案的控制单元和方法
公开(公告)号：US20050212793A1
公开(公告)日：2005-09-29
申请号：US11071537
申请日：2005-03-03
申请人： Oliver Engelhardt , Andreas Eckhardt
发明人： Oliver Engelhardt , Andreas Eckhardt
IPC分类号： G09G5/00
CPC分类号： G09G3/2092 , G09G3/3648 , G09G5/18 , G09G2310/08 , G09G2330/06 , H03L7/197
摘要： A control unit and a method are provided to reduce an interference pattern in the display of an image on a screen with a pixel frequency. The image is described by pixel data and provided to the screen by a control unit. During the generation of pixel data, the clock signals used in the generation of the pixel data are varied or the pixel frequency is changed.
摘要翻译：提供一种控制单元和方法，以减少具有像素频率的屏幕上的图像的显示中的干涉图案。图像由像素数据描述并由控制单元提供给屏幕。在像素数据的生成期间，用于生成像素数据的时钟信号被改变或者像素频率被改变。

58. 发明授权

US06727773B2 Method of generating a clock, a clock generation device, and electronic apparatuses having a clock generation device 失效
标题翻译：时钟生成方法，时钟生成装置以及具有时钟生成装置的电子装置
公开(公告)号：US06727773B2
公开(公告)日：2004-04-27
申请号：US10145241
申请日：2002-05-13
申请人： Masayu Fujiwara
发明人： Masayu Fujiwara
IPC分类号： H03C306
CPC分类号： H03L7/197 , H03K3/0231 , H03K4/502 , H03L7/18 , H04B15/04 , H04B2215/064 , H04B2215/067
摘要： In generating a frequency-modulated clock, a first frequency modulation (FM) signal having frequency fm1 is frequency-modulated by a second FM signal having a second frequency fm2, generating a clock modulation signal fm0. The clock generation signal fm0 is used to frequency-modulate the system clock CLK by the clock modulation signal fm0. Thus, the spectrum of the clock is doubly dispersed by the first and the second FM frequencies. As a result, peak levels at the fundamental and higher harmonic frequencies are reduced as compared with conventional clock generation device.
摘要翻译：在产生调频时钟时，具有频率fm1的第一频率调制（FM）信号由具有第二频率fm2的第二FM信号进行频率调制，产生时钟调制信号fm0。时钟产生信号fm0用于通过时钟调制信号fm0对系统时钟CLK进行频率调制。因此，时钟的频谱被第一和第二FM频率双重分散。结果，与传统的时钟发生装置相比，基波和高次谐波频率的峰值电平降低。

59. 发明申请

US20040071251A1 Clock offset compensator 有权
标题翻译：时钟偏移补偿器
公开(公告)号：US20040071251A1
公开(公告)日：2004-04-15
申请号：US10267177
申请日：2002-10-09
申请人： Marvell International Ltd.
发明人： Henri Sutioso , Lei Wu
IPC分类号： H03D003/24 , H04L007/00
CPC分类号： G06F1/10 , H03L7/081 , H03L7/197 , H04L7/0337
摘要： A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.
摘要翻译：设备与主机通信，并且包括产生本地时钟频率的发射机，接收机和时钟发生器。时钟恢复电路与接收机通信，并从接收机从主机接收的数据恢复主机时钟频率。频率偏移电路与时钟恢复电路和时钟发生器通信，并且基于时钟频率和恢复的主机时钟频率产生频率偏移。频率补偿器使用频率偏移补偿发射机的频率。主机和设备可以使用串行ATA标准进行通信。可以在扩频操作期间进行频率补偿。

60. 发明授权

US06700446B2 Phase-locked loop frequency synthesizer including controllable synchronous frequency dividers controlled by a common frequency dividing control signal 有权
标题翻译：锁相环频率合成器包括由公共分频控制信号控制的可控同步分频器
公开(公告)号：US06700446B2
公开(公告)日：2004-03-02
申请号：US10104957
申请日：2002-03-19
申请人： Ling-Wei Ke
发明人： Ling-Wei Ke
IPC分类号： H03L700
CPC分类号： H03L7/197 , H03L7/0891 , H03L7/095 , H03L7/1972 , Y10S331/02
摘要： A phase-locked loop frequency synthesizer includes a first variable frequency divider connected between a reference signal generator and a first controllable synchronous frequency divider. A second frequency divider is connected between a second controllable synchronous frequency divider and a voltage controlled oscillator. A phase-frequency comparator compares first and second low frequency signals from the first and second controllable synchronous frequency dividers and outputs an adjust signal according to a detected difference therebetween. A phase-locked detector outputs a phase-locked signal in response to the adjust signal. A switching control logic is operable so as to supply a frequency dividing control signal to the first and second controllable synchronous frequency dividers with reference to a divided reference signal from the first variable frequency divider upon receiving the phase-locked signal from the phase-locked detector.
摘要翻译：锁相环频率合成器包括连接在参考信号发生器和第一可控同步分频器之间的第一可变分频器。第二分频器连接在第二可控同步分频器和压控振荡器之间。相位比较器比较来自第一和第二可控同步分频器的第一和第二低频信号，并根据它们之间检测的差异输出调整信号。锁相检测器响应于调节信号输出锁相信号。切换控制逻辑可操作以便在从锁相检测器接收到锁相信号时，参考来自第一可变分频器的分频参考信号，向第一和第二可控同步分频器提供分频控制信号。

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