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51. 发明申请

US20070010055A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20070010055A1
公开(公告)日：2007-01-11
申请号：US11180117
申请日：2005-07-11
申请人： Jongoh Kim , Yider Wu , Kent-Kuohua Chang
发明人： Jongoh Kim , Yider Wu , Kent-Kuohua Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive: layers are formed between two neighboring first dielectric layers in the same row.
摘要翻译：提供了一种制造非易失性存储器的方法。在衬底上形成多个隔离结构的列。在衬底上形成多个跨越隔离结构的层叠栅极结构的行。在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。在堆叠栅极结构的侧壁上形成多个隔离条。多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。在同一行中的两个相邻的第一介电层之间形成多个第一导电层。

52. 发明授权

US07151027B1 Method and device for reducing interface area of a memory device 有权
标题翻译：用于减少存储器件的接口面积的方法和装置
公开(公告)号：US07151027B1
公开(公告)日：2006-12-19
申请号：US10859369
申请日：2004-06-01
申请人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11536 , H01L27/11548
摘要： A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.
摘要翻译：一种用于减少存储器件的接口面积的方法和装置。在存储器阵列和存储器件的外围之间的界面处，在衬底上形成多晶硅层2。聚二层蚀刻到存储器阵列附近。聚二层被蚀刻到外围附近，使得多2层的一部分保留在界面处。

53. 发明申请

US20060270142A1 Method of fabricating memeory 有权
标题翻译：制作方法
公开(公告)号：US20060270142A1
公开(公告)日：2006-11-30
申请号：US11138612
申请日：2005-05-25
申请人： Kent Chang , Jongoh Kim , Yider Wu
发明人： Kent Chang , Jongoh Kim , Yider Wu
IPC分类号： H01L21/8244
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.
摘要翻译：描述了一种制造存储器件的方法。在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

54. 发明授权

US06919247B1 Method of fabricating a floating gate 失效
标题翻译：制造浮栅的方法
公开(公告)号：US06919247B1
公开(公告)日：2005-07-19
申请号：US10655936
申请日：2003-09-04
申请人： Yider Wu , Kuo-Tung Chang
发明人： Yider Wu , Kuo-Tung Chang
IPC分类号： H01L21/28 , H01L21/8247
CPC分类号： H01L21/28273
摘要： A method of fabricating a floating gate for a semiconductor device is disclosed and provided. According to this method, an undoped polycrystalline silicon layer is deposited on a tunnel oxide layer. The undoped polycrystalline silicon layer has a first thickness. Moreover, a doped polycrystalline silicon layer is deposited on the undoped polycrystalline silicon layer. The doped polycrystalline silicon layer has a second thickness. The undoped polycrystalline silicon layer and the doped polycrystalline silicon layer form the floating gate having a third thickness. In an embodiment, the semiconductor device is a flash memory device.
摘要翻译：公开并提供了制造用于半导体器件的浮栅的方法。根据该方法，在隧道氧化物层上沉积未掺杂的多晶硅层。未掺杂的多晶硅层具有第一厚度。此外，掺杂的多晶硅层沉积在未掺杂的多晶硅层上。掺杂多晶硅层具有第二厚度。未掺杂多晶硅层和掺杂多晶硅层形成具有第三厚度的浮动栅极。在一个实施例中，半导体器件是闪存器件。

55. 发明申请

US20050151265A1 Efficient use of wafer area with device under the pad approach 审中-公开
标题翻译：利用垫片方式下的设备有效利用晶圆区域
公开(公告)号：US20050151265A1
公开(公告)日：2005-07-14
申请号：US10758148
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
IPC分类号： G06F17/50 , H01L23/485 , H01L27/02 , H01L23/48 , H01L21/44
CPC分类号： H01L27/0203 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.
摘要翻译：通过在半导体结构的焊盘区域的下方并入有源器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层的下方。有源器件位于第二金属层下方的衬底中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到活动组件。随后的金属层可以布置在第一和第二金属层之间。

56. 发明授权

US06869844B1 Method and structure for protecting NROM devices from induced charge damage during device fabrication 有权
标题翻译：在器件制造期间保护NROM器件免受诱发电荷损伤的方法和结构
公开(公告)号：US06869844B1
公开(公告)日：2005-03-22
申请号：US10701780
申请日：2003-11-05
申请人： Zhizheng Liu , Yider Wu , Jean Yee-Mei Yang
发明人： Zhizheng Liu , Yider Wu , Jean Yee-Mei Yang
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/02 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , H01L27/0248 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.
摘要翻译：描述了在器件制造期间保护NROM免受感应电荷损伤的结构。该结构提供了在制造期间积聚在多晶硅层上的电荷的放电路径，同时提供足够的隔离以确保正常的电路操作。

57. 发明授权

US06754106B1 Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory 有权
标题翻译：具有补偿非易失性存储器中的源极负载效应的各种负载电路的参考电池
公开(公告)号：US06754106B1
公开(公告)日：2004-06-22
申请号：US10245146
申请日：2002-09-16
申请人： Yider Wu , Jean Yang , Jiang Li
发明人： Yider Wu , Jean Yang , Jiang Li
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.
摘要翻译：用于补偿非易失性存储器中源侧负载效应的负载电路。具体地，本发明的实施例描述了耦合到多个负载电路的参考单元。多个负载电路中的至少一个负载电路包括耦合到串联耦合的m个电阻器的选择晶体管。第m个负载电路将位于m个存储单元的相应的第m个存储器单元的源极负载效应与源极线上的源极线节点耦合，该源极线耦合存储器单元的行的存储器单元中的源极区域。

58. 发明授权

US06628545B1 Memory circuit for suppressing bit line current leakage 有权
标题翻译：用于抑制位线电流泄漏的存储电路
公开(公告)号：US06628545B1
公开(公告)日：2003-09-30
申请号：US10306080
申请日：2002-11-26
申请人： Jiang Li , Yider Wu , Zhizheng Liu
发明人： Jiang Li , Yider Wu , Zhizheng Liu
IPC分类号： G11C1604
CPC分类号： G11C16/3404
摘要： A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.
摘要翻译：公开了一种在存储器件中使用的存储器电路。根据一个实施例，存储器电路包括第一存储单元和第二存储单元。第一存储单元具有连接到位线的漏极端子，该位线连接到感测电路。第一存储单元还具有连接到字线的控制栅极。第二存储单元还具有连接到位线的漏极端子。第二存储单元的控制栅极接地。存储器电路将大于接地电压的源极电压提供给第一存储单元的源极端子和第二存储器单元的源极端子，使得第二存储器单元的栅极 - 源极电压小于阈值第二存储单元的电压。

59. 发明授权

US06395654B1 Method of forming ONO flash memory devices using rapid thermal oxidation 有权
标题翻译：使用快速热氧化形成ONO闪存器件的方法
公开(公告)号：US06395654B1
公开(公告)日：2002-05-28
申请号：US09648077
申请日：2000-08-25
申请人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
发明人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
IPC分类号： H01L21225
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。将氮注入到第一层氧化硅中，然后使用快速热工具来加热半导体结构，以退出植入物损伤并将植入的氮扩散到衬底和氧化硅界面，以在该位置形成SiN键接口。 SiN键是期望的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

60. 发明授权

US08598645B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US08598645B2
公开(公告)日：2013-12-03
申请号：US12910331
申请日：2010-10-22
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

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