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1. 外观设计

USD668139S1 Packaging for a hand tool 有权
标题翻译：手工包装
公开(公告)号：USD668139S1
公开(公告)日：2012-10-02
申请号：US29398096
申请日：2011-07-26
申请人： Da Nian Yang , Mark Holtan
设计人： Da Nian Yang , Mark Holtan

2. 外观设计

USD661166S1 Wrench 有权
公开(公告)号：USD661166S1
公开(公告)日：2012-06-05
申请号：US29407421
申请日：2011-11-29
申请人： Brent Christopher , Da Nian Yang , Hua An Xu
设计人： Brent Christopher , Da Nian Yang , Hua An Xu

3. 发明授权

US07948820B2 Circuit pre-charge to sense a memory line 有权
标题翻译：电路预充电以感测存储线
公开(公告)号：US07948820B2
公开(公告)日：2011-05-24
申请号：US11951262
申请日：2007-12-05
申请人： Tien-Chun Yang , Yonggang Wu , Nian Yang
发明人： Tien-Chun Yang , Yonggang Wu , Nian Yang
IPC分类号： G11C7/00
CPC分类号： G11C16/30 , G11C7/12 , G11C16/24
摘要： Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.
摘要翻译：通常，存储线的读取时间由于电压过冲和/或电压下冲而变慢。为了消除这些问题，控制部件可以管理电压，同时泄漏部件管理电压的时序。这允许产生增加读取时间的线路预充电。控制组件可以实现一个可变电阻器来修改值来补偿温度。泄漏部件可以包括允许电压通过的电容器配置。

4. 发明授权

US07808827B2 Controlled bit line discharge for channel erases in nonvolatile memory 有权
标题翻译：非易失性存储器中的通道擦除控制位线放电
公开(公告)号：US07808827B2
公开(公告)日：2010-10-05
申请号：US11935717
申请日：2007-11-06
申请人： Aaron Lee , Nian Yang , Jiani Zhang
发明人： Aaron Lee , Nian Yang , Jiani Zhang
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C11/5635 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.
摘要翻译：提出了有助于以受控的速率放电与非易失性存储器中的存储器阵列相关联的位线（BL）的系统和/或方法。放电元件有助于以期望的速率放电BL，从而防止在与非易失性存储器相关联的y解码器组件内发生“热切换”现象。放电部件可以部分地由控制BL放电速率的放电晶体管部件组成，其中放电晶体管部件的栅极电压可以由放电控制器部件控制。 BL放电的速率可以由设计中使用的放电晶体管组件的大小，y解码器组件的强度和/或尺寸，特定存储器件发生的擦除错误的数量和/或其他因素，以便于防止发生热切换。

5. 发明授权

US07632749B1 Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer 有权
标题翻译：具有电耦合的焊盘金属层和下金属层的半导体器件，而在焊盘金属层的中心区域下方的下金属层中形成孔
公开(公告)号：US07632749B1
公开(公告)日：2009-12-15
申请号：US10823970
申请日：2004-04-13
申请人： Hiroyuki Ogawa , Yider Wu , Nian Yang , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Nian Yang , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.
摘要翻译：公开并提供了半导体器件。半导体器件包括具有周边区域和中心区域的焊盘金属层。此外，半导体器件具有在焊盘金属层的中心区域下方具有多个孔的下部金属层。此外，在焊盘金属层和下金属层之间形成层间电介质。在一个实施例中，半导体器件还包括形成在层间电介质中的多个通孔。通孔电连接焊盘金属层和下部金属层。另外，通孔位于垫金属层的周边区域的下方。

6. 发明申请

US20090273998A1 BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF 有权
标题翻译： BITCELL电流检测器件及其方法
公开(公告)号：US20090273998A1
公开(公告)日：2009-11-05
申请号：US12114966
申请日：2008-05-05
申请人： Hongtau Mu , Nian Yang , Fan Wan Lai , Guowei Wang
发明人： Hongtau Mu , Nian Yang , Fan Wan Lai , Guowei Wang
IPC分类号： G11C7/06
CPC分类号： G11C7/067 , G11C7/062 , G11C7/08 , G11C2207/063
摘要： A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.
摘要翻译：存储器件包括用于感测位单元的状态的读出放大器。读出放大器包括通过开关连接的两个输入端。一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

7. 发明申请

US20090206386A1 DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES 有权
标题翻译：适用于闪存存储器件充电保护的解码系统
公开(公告)号：US20090206386A1
公开(公告)日：2009-08-20
申请号：US12034316
申请日：2008-02-20
申请人： Nian Yang , Joon-Heong Ong , Jiani Zhang
发明人： Nian Yang , Joon-Heong Ong , Jiani Zhang
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11573 , H01L27/11565 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level. Other methods and circuits are also disclosed.
摘要翻译：本发明的一个实施例涉及闪存阵列。闪存阵列包括栅电极材料的至少两个字线。至少一个字线通过第一金属电平连接到放电电路，而其它字线可以通过第一和第二金属电平连接到放电电路。存储器阵列还包括存储器阵列的字线之间的短路。短路路径是未掺杂的栅电极材料的高电阻层。栅极材料的电阻值使得字线可以用于读取，写入或擦除而不会彼此影响，但是在形成第一金属电平期间，由于电荷将在第一字线上积累这要求第二金属电平连接到其放电结电路，它将使第一字线缩短到与第一金属电平上的结电路连接的相邻第二字线。还公开了其它方法和电路。

8. 发明申请

US20080266926A1 TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES 有权
标题翻译：在闪存存储器件上传输非相关信息
公开(公告)号：US20080266926A1
公开(公告)日：2008-10-30
申请号：US11741996
申请日：2007-04-30
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C5/06
CPC分类号： G11C8/12 , G11C7/12 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.
摘要翻译：描述了通过存储器阵列在闪速存储器件内传送信息的方式。控制器从存储单元检索信息，然后解码器解码该信息。信息通过一个通过门到一个第二个控制器的一系列位线设置。位线都与存储单元相关联，以及与其他存储单元相关联的位线。一系列晶体管与每个位线相关联。基于如果位线与当前使用的存储单元相关联，不同的晶体管是有效的。

9. 发明授权

US07443732B2 High performance flash memory device capable of high density data storage 有权
标题翻译：高性能闪存设备能够进行高密度数据存储
公开(公告)号：US07443732B2
公开(公告)日：2008-10-28
申请号：US11229527
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael A. VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Quang Le
发明人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael A. VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Quang Le
IPC分类号： G11C11/34
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。预定数量的位同时被编程到阵列中的对应存储器单元。同时验证阵列中预定位数的编程状态。

10. 发明申请

US20080130371A1 METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20080130371A1
公开(公告)日：2008-06-05
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C16/12 , G11C16/28
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

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