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51. 发明申请

US20100275174A1 Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件图案生成方法，图案数据处理方法，图案数据处理程序和半导体器件制造方法
公开(公告)号：US20100275174A1
公开(公告)日：2010-10-28
申请号：US12801895
申请日：2010-06-30
申请人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
发明人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.
摘要翻译：从包含半导体集成电路的图案的第一设计数据中提取尺寸不大于阈值的校正对象图案。基于第一设计数据计算半导体集成电路的第一特性。通过校正包含在第一设计数据中的校正目标图案来生成第二设计数据。基于第二设计数据计算半导体集成电路的第二特性。检查第一特性和第二特性之间的特性差是否落在公差之内。当特性差在公差范围内时，决定使用第二设计数据来制造半导体集成电路。

52. 发明授权

US09207531B2 Pattern forming method 有权
标题翻译：图案形成方法
公开(公告)号：US09207531B2
公开(公告)日：2015-12-08
申请号：US13239449
申请日：2011-09-22
申请人： Hiroko Nakamura , Koji Asakawa , Shigeki Hattori , Satoshi Tanaka , Toshiya Kotani
发明人： Hiroko Nakamura , Koji Asakawa , Shigeki Hattori , Satoshi Tanaka , Toshiya Kotani
IPC分类号： H01L21/31 , H01L21/469 , G03F7/00 , B81C1/00 , B82Y10/00 , B82Y40/00
CPC分类号： G03F7/0002 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y40/00
摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.
摘要翻译：根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案，区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。用左图案蚀刻该胶片作为掩模。

53. 发明授权

US08122385B2 Mask pattern correcting method 有权
标题翻译：掩模图案校正方法
公开(公告)号：US08122385B2
公开(公告)日：2012-02-21
申请号：US12129167
申请日：2008-05-29
申请人： Kazuya Fukuhara , Tatsuhiko Higashiki , Toshiya Kotani , Satoshi Tanaka , Takashi Sato , Akiko Mimotogi , Masaki Satake
发明人： Kazuya Fukuhara , Tatsuhiko Higashiki , Toshiya Kotani , Satoshi Tanaka , Takashi Sato , Akiko Mimotogi , Masaki Satake
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.
摘要翻译：在基于模型的OPC中，使用光学图像强度模拟器对每个掩模图案进行适当的掩模校正，将掩模图案划分为子区域，并且根据每个子区域中的图案的内容来改变光学图像强度模拟模型。当掩模图案的最小尺寸小于在曝光波长附近设置的特定阈值时，使用高精度模型计算该区域，并且使用高速模型来计算其它区域。

54. 发明授权

US07669172B2 Pattern creation method, mask manufacturing method and semiconductor device manufacturing method 失效
标题翻译：图案形成方法，掩模制造方法和半导体器件制造方法
公开(公告)号：US07669172B2
公开(公告)日：2010-02-23
申请号：US12050764
申请日：2008-03-18
申请人： Takeshi Ito , Satoshi Tanaka , Toshiya Kotani , Tadahito Fujisawa , Koji Hashimoto
发明人： Takeshi Ito , Satoshi Tanaka , Toshiya Kotani , Tadahito Fujisawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F1/00
摘要： A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.
摘要翻译：一种图案创建方法，包括在第一层上布置集成电路图案的最极端格式的数据，并且在第二层上布置不包括最末端图案的集成电路图案的数据，提取第一最接近的数据图案最接近于来自第二层的最末端图案，并将所提取的数据转换为第三层，产生在第四层中接触第一最近图案和最末端图案的接触图案的数据，产生接触图案的非重叠图案的数据，不包括在第五层中具有最末端图案和最前端图案和第一最近图案的重叠部分，提取最接近图案的第二最接近图案的数据，其最接近非重叠图案并且转换提取的数据到第一层。

55. 发明授权

US07200833B2 Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method 失效
标题翻译：边缘偏移量的计算方法，验证方法，验证程序和验证系统以及半导体器件制造方法
公开(公告)号：US07200833B2
公开(公告)日：2007-04-03
申请号：US10801798
申请日：2004-03-17
申请人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G03F7/705
摘要： A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.
摘要翻译：将期望图案与根据设计图案预测的要在晶片上形成的光洁度图案进行比较的方法，基于光束强度的计算和完成图案与期望图案的偏差量在完成图案的每个边缘处并计算所需图案，包括设置用于在晶片上设置期望图案的参考光束强度，设置用于将完成图案与期望图案进行比较的评估点，计算光束强度在评价点，计算评价点的光束强度的微分值，计算微分值与参考光束强度的交点，计算交点与评价点之间的差，限定边缘的差完成图案与期望图案的偏差量。

56. 发明申请

US20050153217A1 Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method 失效
标题翻译：模式验证方法，模式验证系统，掩模制造方法和半导体器件制造方法
公开(公告)号：US20050153217A1
公开(公告)日：2005-07-14
申请号：US11012494
申请日：2004-12-16
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G03F9/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：一种图案验证方法，包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个工艺参数以计算所转印/形成的图案，定义对于每个过程参数的参考值和可变范围，计算与评估点相对应的每个第一点的位置位移，使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合可变范围或在各个可变范围内，位置偏移是第一点和评估点之间的位移，计算每个评估点的位置偏移的统计，以及根据统计信息输出修改掩模图案的信息。

57. 发明申请

US20050064302A1 Method and system for forming a mask pattern, method of manufacturing a semiconductor device, system forming a mask pattern on data, cell library and method of forming a photomask 失效
标题翻译：用于形成掩模图案的方法和系统，制造半导体器件的方法，在数据上形成掩模图案的系统，单元库和形成光掩模的方法
公开(公告)号：US20050064302A1
公开(公告)日：2005-03-24
申请号：US10933334
申请日：2004-09-03
申请人： Toshiya Kotani , Satoshi Tanaka , Shoichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shoichi Inoue
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01J37/302 , H01L21/027 , G03F9/00 , G21K5/10 , H01J37/08
CPC分类号： G03F1/36 , H01J37/3026 , H01J2237/31769
摘要： A method of forming a mask pattern comprises the following steps. A second cell library is prepared by making process proximity effect correction with respect to cell patterns stored in a first cell library. The second cell library stores corrected cell patterns. A first corrected cell pattern and a second corrected cell pattern of the corrected cell patterns are placed so that an edge of the first corrected cell pattern and an edge of the second corrected cell pattern contact or come close to or overlap each other. A boundary pattern at the boundary neighborhood between the first corrected cell pattern and the second corrected cell pattern is extracted. Process proximity effect correction is made with respect to the boundary pattern.
摘要翻译：形成掩模图案的方法包括以下步骤。通过相对于存储在第一个细胞库中的细胞图案进行过程接近效应校正来制备第二个细胞库。第二个细胞库存储校正的细胞图案。放置经校正的单元图案的第一校正单元图案和第二校正单元图形，使得第一校正单元图案的边缘和第二校正单元图案的边缘彼此接近或重叠。提取在第一校正单元图案和第二校正单元图案之间的边界邻域处的边界图案。相对于边界图案进行过程接近效应校正。

58. 发明授权

US08527914B2 Flare map calculating method and recording medium 有权
标题翻译：耀斑图计算方法和记录介质
公开(公告)号：US08527914B2
公开(公告)日：2013-09-03
申请号：US13615691
申请日：2012-09-14
申请人： Taiga Uno , Toshiya Kotani , Satoshi Tanaka
发明人： Taiga Uno , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70941 , G03F1/70
摘要： A flare map calculating method of an embodiment calculates an optical image intensity distribution in each division region set in a pattern region. Furthermore, an average value of the optical image intensity distribution is calculated in each division region. A pattern or plural patterns, which has a pattern density corresponding to the average value, is calculated as a corresponding density pattern in each division region. Furthermore, a density map, which represents a pattern density distribution within the pattern region, is generated based on the corresponding density pattern, and a flare map representing a flare intensity distribution within the pattern region is calculated by convolution integral of the density map and a point spread function.
摘要翻译：实施例的耀斑映射计算方法计算在图案区域中设置的每个划分区域中的光学图像强度分布。此外，在每个划分区域中计算出光学图像强度分布的平均值。在每个划分区域中计算具有对应于平均值的图案密度的图案或多个图案作为相应的浓度图案。此外，基于对应的浓度模式生成表示图案区域内的图案密度分布的密度图，并且通过密度图和a的卷积积分来计算表示图案区域内的耀斑强度分布的耀斑图点扩散功能。

59. 发明授权

US08112167B2 Process controller for semiconductor manufacturing, utilizing dangerous pattern identification and process capability determination 有权
标题翻译：用于半导体制造的过程控制器，利用危险模式识别和过程能力确定
公开(公告)号：US08112167B2
公开(公告)日：2012-02-07
申请号：US12354574
申请日：2009-01-15
申请人： Ayako Endo , Kenji Yoshida , Toshiya Kotani , Satoshi Tanaka
发明人： Ayako Endo , Kenji Yoshida , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G05B19/41865 , G05B19/41885 , H01L22/20 , H01L2924/0002 , Y02P90/20 , Y02P90/26 , H01L2924/00
摘要： A process control method comprises adjusting a process condition in consideration of a performance variation among a plurality of manufacturing apparatuses, the performance variation affecting a finished shape of a pattern used to manufacture a semiconductor device, running a simulation of the finished shape under the adjusted process condition, extracting a dangerous point of the pattern affecting satisfaction from the result of the simulation, comparing a first process capability serving as a judgment standard to find whether a production schedule of the device is achieved with a second capability serving to form a dangerous pattern containing the dangerous point, and improving the second process when the second process capability is lower than the first process capability.
摘要翻译：一种过程控制方法包括考虑多个制造装置之间的性能变化来调整工艺条件，影响用于制造半导体器件的图案的成品形状的性能变化，在调整过程下运行成品形状的模拟从模拟结果中提取影响满意度的模式的危险点，比较作为判断标准的第一处理能力，以确定是否实现具有第二能力的设备的生产计划，以形成含有危险点，并且当第二处理能力低于第一处理能力时，改进第二过程。

60. 发明申请

US20100082144A1 METHOD OF CALCULATING PATTERN-FAILURE-OCCURRENCE-REGION, COMPUTER PROGRAM PRODUCT, PATTERN-LAYOUT EVALUATING METHOD, AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD 有权
标题翻译：计算图形失效区域的方法，计算机程序产品，图案布局评估方法和半导体器件制造方法
公开(公告)号：US20100082144A1
公开(公告)日：2010-04-01
申请号：US12554495
申请日：2009-09-04
申请人： Masanori TAKAHASHI , Toshiya Kotani , Satoshi Tanaka
发明人： Masanori TAKAHASHI , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G06F17/5081
摘要： Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.
摘要翻译：计算图案故障发生区域的方法包括使用关系信息和用于形成凸部的布局来计算图案故障发生区域，所述关系信息是从胶片中形成的图案到覆盖凸起的距离之间的关系由于凸部的影响，形成图案的形状不能满足规定条件的膜中的与凸部的基板上的区域。

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