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1. 发明授权

US09207531B2 Pattern forming method 有权
标题翻译：图案形成方法
公开(公告)号：US09207531B2
公开(公告)日：2015-12-08
申请号：US13239449
申请日：2011-09-22
申请人： Hiroko Nakamura , Koji Asakawa , Shigeki Hattori , Satoshi Tanaka , Toshiya Kotani
发明人： Hiroko Nakamura , Koji Asakawa , Shigeki Hattori , Satoshi Tanaka , Toshiya Kotani
IPC分类号： H01L21/31 , H01L21/469 , G03F7/00 , B81C1/00 , B82Y10/00 , B82Y40/00
CPC分类号： G03F7/0002 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y40/00
摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.
摘要翻译：根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案，区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。用左图案蚀刻该胶片作为掩模。

2. 发明申请

US20120127454A1 PATTERN FORMING METHOD 有权
标题翻译：图案形成方法
公开(公告)号：US20120127454A1
公开(公告)日：2012-05-24
申请号：US13239449
申请日：2011-09-22
申请人： Hiroko NAKAMURA , Koji Asakawa , Shigeki Hattori , Satoshi Tanaka , Toshiya Kotani
发明人： Hiroko NAKAMURA , Koji Asakawa , Shigeki Hattori , Satoshi Tanaka , Toshiya Kotani
IPC分类号： G03B27/32
CPC分类号： G03F7/0002 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y40/00
摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.
摘要翻译：根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案，区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。用左图案蚀刻该胶片作为掩模。

3. 发明申请

US20120214094A1 METHOD OF FORMING PATTERN 有权
标题翻译：形成图案的方法
公开(公告)号：US20120214094A1
公开(公告)日：2012-08-23
申请号：US13402400
申请日：2012-02-22
申请人： Satoshi MIKOSHIBA , Koji Asakawa , Hiroko Nakamura , Shigeki Hattori , Atsushi Hieno , Tsukasa Azuma , Yuriko Seino , Masahiro Kanno
发明人： Satoshi MIKOSHIBA , Koji Asakawa , Hiroko Nakamura , Shigeki Hattori , Atsushi Hieno , Tsukasa Azuma , Yuriko Seino , Masahiro Kanno
IPC分类号： G03F7/20 , H01L21/302 , G03F7/00
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , G03F7/0757 , G03F7/165 , G03F7/26 , H01L21/3086
摘要： According to one embodiment, there is provided a method of forming a pattern including forming a polymer layer on a substrate, the polymer layer including a first and second regions, selectively irradiating either of the first and second regions with energy rays or irradiating the first and second regions with energy rays under different conditions to cause a difference in surface free energy between the first and second regions, thereafter, forming a block copolymer layer on the polymer layer, and causing microphase separation in the block copolymer layer to simultaneously form first and second microphase-separated structures on the first and second regions, respectively.
摘要翻译：根据一个实施方案，提供了一种形成图案的方法，包括在基底上形成聚合物层，聚合物层包括第一和第二区域，用能量射线选择性地照射第一和第二区域中的任一个，或者照射第一和第二区域在不同条件下具有能量射线的第二区域引起第一和第二区域之间的表面自由能的差异，此后在聚合物层上形成嵌段共聚物层，并且使嵌段共聚物层中的微相分离同时形成第一和第二分别在第一和第二区域上的微相分离结构。

4. 发明授权

US08808973B2 Method of forming pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US08808973B2
公开(公告)日：2014-08-19
申请号：US13402400
申请日：2012-02-22
申请人： Satoshi Mikoshiba , Koji Asakawa , Hiroko Nakamura , Shigeki Hattori , Atsushi Hieno , Tsukasa Azuma , Yuriko Seino , Masahiro Kanno
发明人： Satoshi Mikoshiba , Koji Asakawa , Hiroko Nakamura , Shigeki Hattori , Atsushi Hieno , Tsukasa Azuma , Yuriko Seino , Masahiro Kanno
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , G03F7/0757 , G03F7/165 , G03F7/26 , H01L21/3086
摘要： According to one embodiment, there is provided a method of forming a pattern including forming a polymer layer on a substrate, the polymer layer including a first and second regions, selectively irradiating either of the first and second regions with energy rays or irradiating the first and second regions with energy rays under different conditions to cause a difference in surface free energy between the first and second regions, thereafter, forming a block copolymer layer on the polymer layer, and causing microphase separation in the block copolymer layer to simultaneously form first and second microphase-separated structures on the first and second regions, respectively.
摘要翻译：根据一个实施方案，提供了一种形成图案的方法，包括在基底上形成聚合物层，聚合物层包括第一和第二区域，用能量射线选择性地照射第一和第二区域中的任一个，或者照射第一和第二区域在不同条件下具有能量射线的第二区域引起第一和第二区域之间的表面自由能的差异，此后在聚合物层上形成嵌段共聚物层，并且使嵌段共聚物层中的微相分离同时形成第一和第二分别在第一和第二区域上的微相分离结构。

5. 发明授权

US09073284B2 Method of forming pattern and laminate 有权
标题翻译：形成图案和层压板的方法
公开(公告)号：US09073284B2
公开(公告)日：2015-07-07
申请号：US13626415
申请日：2012-09-25
申请人： Atsushi Hieno , Shigeki Hattori , Hiroko Nakamura , Satoshi Mikoshiba , Koji Asakawa , Masahiro Kanno , Yuriko Seino , Tsukasa Azuma
发明人： Atsushi Hieno , Shigeki Hattori , Hiroko Nakamura , Satoshi Mikoshiba , Koji Asakawa , Masahiro Kanno , Yuriko Seino , Tsukasa Azuma
IPC分类号： B32B7/04 , B82Y30/00 , G03F7/004 , G03F7/20 , G03F7/075 , G03F7/11 , G03F7/16 , G03F7/40
CPC分类号： G03F7/40 , B32B7/04 , B32B2307/40 , B82Y30/00 , G03F7/0002 , G03F7/004 , G03F7/0751 , G03F7/0752 , G03F7/11 , G03F7/165 , G03F7/20
摘要： According to one embodiment, there is provided a method of forming a pattern, including forming a thermally crosslinkable molecule layer including a thermally crosslinkable molecule on a substrate, forming a photosensitive composition layer including a photosensitive composition on the thermally crosslinkable molecule layer, chemically binding the thermally crosslinkable molecule to the photosensitive composition by heating, selectively irradiating the photosensitive composition layer with energy rays, forming a block copolymer layer including a block copolymer on the photosensitive composition layer, and forming a microphase-separated structure in the block copolymer layer.
摘要翻译：根据一个实施方案，提供了形成图案的方法，包括在基材上形成包含热交联性分子的热交联性分子层，在热交联性分子层上形成包含感光性组合物的感光性组合物层，化学结合热交联性分子通过加热，用能量射线选择性地照射感光性组合物层，在感光性组合物层上形成包含嵌段共聚物的嵌段共聚物层，在嵌段共聚物层中形成微相分离结构。

6. 发明授权

US08896052B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08896052B2
公开(公告)日：2014-11-25
申请号：US13727160
申请日：2012-12-26
申请人： Misako Morota , Hideyuki Nishizawa , Masaya Terai , Shigeki Hattori , Koji Asakawa
发明人： Misako Morota , Hideyuki Nishizawa , Masaya Terai , Shigeki Hattori , Koji Asakawa
IPC分类号： H01L29/792 , H01L21/28 , H01L29/51 , H01L29/66 , H01L27/115
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
摘要翻译：实施例的非易失性半导体存储器件包括：半导体层; 隧道绝缘膜，其形成在所述半导体层上并且包括第一有机分子膜，所述第一有机分子膜包含以烷基分子链为主链的第一有机分子; 形成在隧道绝缘膜上的电荷存储层，电荷存储层由无机材料制成; 形成在电荷存储层上的块绝缘膜; 以及形成在所述块绝缘膜上的控制栅电极。

7. 发明授权

US08890234B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08890234B2
公开(公告)日：2014-11-18
申请号：US13721860
申请日：2012-12-20
申请人： Masaya Terai , Shigeki Hattori , Hideyuki Nishizawa , Koji Asakawa , Tsukasa Tada
发明人： Masaya Terai , Shigeki Hattori , Hideyuki Nishizawa , Koji Asakawa , Tsukasa Tada
IPC分类号： H01L29/792 , H01L21/28 , H01L51/05 , H01L27/115 , H01L51/00
CPC分类号： H01L27/11582 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/75 , H01L21/28282 , H01L29/4234 , H01L29/51 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/792 , H01L29/7926 , H01L51/0078 , H01L51/0591
摘要： A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film formed on the semiconductor layer; an organic molecular layer that is formed on the tunnel insulating film, and includes first organic molecules and second organic molecules having a smaller molecular weight than the first organic molecules, the first organic molecules each including a first alkyl chain or a first alkyl halide chain having one end bound to the tunnel insulating film, the first organic molecules each including a charge storage portion bound to the other end of the first alkyl chain or the first alkyl halide chain, the second organic molecules each including a second alkyl chain or a second alkyl halide chain having one end bound to the tunnel insulating film; a block insulating film formed on the organic molecular layer; and a control gate electrode formed on the block insulating film.
摘要翻译：实施例的非易失性半导体存储器件包括：半导体层; 形成在半导体层上的隧道绝缘膜; 形成在所述隧道绝缘膜上的有机分子层，并且包括第一有机分子和具有比所述第一有机分子分子量小的第二有机分子，所述第一有机分子各自包含第一烷基链或第一烷基卤链，所述第一烷基链或第一烷基卤链具有所述第一有机分子各自包含结合到所述第一烷基链或所述第一烷基卤链的另一端的电荷存储部分，所述第二有机分子各自包含第二烷基链或第二烷基卤化物链的一端与隧道绝缘膜结合; 形成在有机分子层上的块绝缘膜; 以及形成在所述块绝缘膜上的控制栅电极。

8. 发明授权

US09047941B2 Organic molecular memory 有权
标题翻译：有机分子记忆
公开(公告)号：US09047941B2
公开(公告)日：2015-06-02
申请号：US13425796
申请日：2012-03-21
申请人： Hideyuki Nishizawa , Reiko Yoshimura , Tsukasa Tada , Shigeki Hattori , Masaya Terai , Satoshi Mikoshiba , Koji Asakawa
发明人： Hideyuki Nishizawa , Reiko Yoshimura , Tsukasa Tada , Shigeki Hattori , Masaya Terai , Satoshi Mikoshiba , Koji Asakawa
IPC分类号： H01L51/10 , H01L29/792 , G11C13/00 , B82Y10/00 , H01L51/00 , H01L51/05
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , G11C2213/53 , H01L45/1233 , H01L45/1253 , H01L51/0078 , H01L51/0092 , H01L51/0098 , H01L51/0595
摘要： An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including charge-storage molecular chains or variable-resistance molecular chains, the charge-storage molecular chains or the variable-resistance molecular chains including fused polycyclic groups.
摘要翻译：实施方案的有机分子存储器包括第一导电层，第二导电层和介于第一导电层和第二导电层之间的有机分子层，有机分子层包括电荷储存分子链或可变电阻分子链，电荷储存分子链或可变阻力分子链，包括稠合多环基团。

9. 发明申请

US20140061763A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20140061763A1
公开(公告)日：2014-03-06
申请号：US13727160
申请日：2012-12-26
申请人： Misako Morota , Hideyuki Nishizawa , Masaya Terai , Shigeki Hattori , Koji Asakawa
发明人： Misako Morota , Hideyuki Nishizawa , Masaya Terai , Shigeki Hattori , Koji Asakawa
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
摘要翻译：实施例的非易失性半导体存储器件包括：半导体层; 隧道绝缘膜，其形成在所述半导体层上并且包括第一有机分子膜，所述第一有机分子膜包含以烷基分子链为主链的第一有机分子; 形成在隧道绝缘膜上的电荷存储层，电荷存储层由无机材料制成; 形成在电荷存储层上的块绝缘膜; 以及形成在所述块绝缘膜上的控制栅电极。

10. 发明授权

US08575587B2 Storage device and method of manufacturing the same 有权
标题翻译：存储装置及其制造方法
公开(公告)号：US08575587B2
公开(公告)日：2013-11-05
申请号：US13236793
申请日：2011-09-20
申请人： Koji Asakawa , Shigeki Hattori , Hideyuki Nishizawa , Satoshi Mikoshiba , Reika Ichihara , Masaya Terai
发明人： Koji Asakawa , Shigeki Hattori , Hideyuki Nishizawa , Satoshi Mikoshiba , Reika Ichihara , Masaya Terai
IPC分类号： H01L47/00 , H01L29/06
CPC分类号： H01L51/0591 , G11C13/0014 , G11C13/003 , G11C2213/72 , G11C2213/73 , G11C2213/77
摘要： A storage device includes: a plurality of first electrode wirings; a plurality of second electrode wirings which cross the first electrode wirings; a via plug which is formed between the second electrode wiring and the two adjacent first electrode wirings, and in which a maximum diameter of a bottom surface opposing the first electrode wirings in a direction vertical to a direction in which the first electrode wirings stretch is smaller than a length corresponding to a pitch of the first electrode wiring plus a width of the first electrode wirings; a first storage element which is formed between the via plug and one of the two first electrode wirings; and a second storage element which is formed between the via plug and the other one of the two first electrode wirings.
摘要翻译：存储装置包括：多个第一电极布线; 与第一电极布线交叉的多个第二电极布线; 形成在所述第二电极布线和所述两个相邻的第一电极布线之间的通孔塞，其中与所述第一电极布线相反的方向上的与所述第一电极相对的底面的最大直径在与所述第一电极布线拉伸的方向垂直的方向上布线的最大直径较小比对应于第一电极布线的间距加上第一电极布线的宽度的长度; 第一存储元件，其形成在所述通孔插头和所述两个第一电极布线中的一个之间; 以及第二存储元件，其形成在所述通孔插头和所述两个第一电极布线中的另一个之间。

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