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51. 发明授权

US06829040B1 Lithography contrast enhancement technique by varying focus with wavelength modulation 有权
标题翻译：通过波长调制改变焦点的平版印刷对比度增强技术
公开(公告)号：US06829040B1
公开(公告)日：2004-12-07
申请号：US10703643
申请日：2003-11-07
申请人： Jongwook Kye , Ivan Lalovic , Christopher F. Lyons , Ramkumar Subramanian
发明人： Jongwook Kye , Ivan Lalovic , Christopher F. Lyons , Ramkumar Subramanian
IPC分类号： G03B2742
CPC分类号： G03F7/70575 , G03F7/703 , G03F7/70333
摘要： A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength band centered about a nominal wavelength on an optic path towards the substrate during an exposure period. A wavelength modulation system within the optic path comprises means for chromatically separating the narrow wavelength band into at least two sub-bands, the first sub-band being smaller than the narrow wavelength band and centered about a first sub-band wavelength and the second sub-band being smaller than the narrow wavelength band and centered about a second sub-band wavelength and means for passing each of the first sub-band and the second sub-band during distinct time periods within the exposure period.
摘要翻译：投影光刻系统在半导体衬底的表面上曝光感光材料，其包括高电平和低电平之间的表面高度变化。该系统包括照射源，其在曝光期间内以在光路上朝着衬底的标称波长为中心的窄波长带内投射照明。光路内的波长调制系统包括用于将窄波段色带分离成至少两个子带的装置，第一子带小于窄波段并以第一子带波长为中心，第二子带带窄于窄波长带并以第二子带波长为中心，以及用于在曝光周期内的不同时间段内通过第一子带和第二子带中的每一个的装置。

52. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

53. 发明授权

US06654660B1 Controlling thermal expansion of mask substrates by scatterometry 有权
标题翻译：通过散射法控制掩模基板的热膨胀
公开(公告)号：US06654660B1
公开(公告)日：2003-11-25
申请号：US10287292
申请日：2002-11-04
申请人： Bhanwar Singh , Christopher F. Lyons , Bharath Rangarajan , Khoi A. Phan , Ramkumar Subramanian
发明人： Bhanwar Singh , Christopher F. Lyons , Bharath Rangarajan , Khoi A. Phan , Ramkumar Subramanian
IPC分类号： G06F1900
CPC分类号： G03F7/70425 , G03F7/70875
摘要： One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.
摘要翻译：本发明的一个方面涉及一种用于在EUV光刻期间控制EUV掩模上的热膨胀的系统和方法。该系统包括用于通过图案化的EUV掩模的一个或多个光栅照射晶片的一个或多个层的EUV光刻系统，由此在图案化的EUV掩模的照射期间在图案化的EUV掩模的至少一部分上积聚热量晶圆; 用于监视所述掩模上的所述一个或多个光栅以检测其中的扩展的EUV掩模检查系统，所述检查系统产生与所述掩模有关的数据; 以及温度控制系统，其可操作地耦合到所述检查系统，以对EUV光刻系统进行调整，以便补偿所述掩模上检测到的膨胀。该方法涉及采用反馈和前馈控制来优化当前和未来的EUV光刻工艺。

54. 发明授权

US06599810B1 Shallow trench isolation formation with ion implantation 有权
标题翻译：浅沟隔离形成与离子注入
公开(公告)号：US06599810B1
公开(公告)日：2003-07-29
申请号：US09186078
申请日：1998-11-05
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L2176
CPC分类号： H01L21/76237 , H01L21/26586 , H01L21/76235
摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
摘要翻译：通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强氧化速率，并因此增加沟槽边缘处氧化物的厚度。实施例包括在生长氧化物衬垫之前的离子注入杂质。沟槽边缘上产生的厚氧化物避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

55. 发明授权

US06326319B1 Method for coating ultra-thin resist films 有权
标题翻译：超薄抗蚀剂膜的涂布方法
公开(公告)号：US06326319B1
公开(公告)日：2001-12-04
申请号：US09609746
申请日：2000-07-03
申请人： Christopher L. Pike , Khanh B. Nguyen , Christopher F. Lyons
发明人： Christopher L. Pike , Khanh B. Nguyen , Christopher F. Lyons
IPC分类号： H01F1002
CPC分类号： H01L21/02312 , G03F7/16 , G03F7/162 , H01L21/02109 , H01L21/02307 , H01L21/312 , H01L21/3125
摘要： There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 18° C. to 50° C. for a short amount of time. This is performed prior to the application of a liquid solvent. As a result, there is overcome the problems of poor adhesion to the substrates and high defect levels in the coated UTR films.
摘要翻译：提供了一种将低粘度涂布液施加到半导体晶片衬底上以防止粘附损失并保持低缺陷水平特性的方法。这是通过用粘合剂在18℃至50℃的温度范围内引发基底短时间来实现的。这是在施加液体溶剂之前进行的。结果，克服了在涂覆的UTR膜中对基材的粘附性差和高缺陷水平的问题。

56. 发明授权

US06287959B1 Deep submicron metallization using deep UV photoresist 失效
标题翻译：深亚微米金属化使用深紫外光致抗蚀剂
公开(公告)号：US06287959B1
公开(公告)日：2001-09-11
申请号：US09065352
申请日：1998-04-23
申请人： Christopher F. Lyons , Bhanwar Singh
发明人： Christopher F. Lyons , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31116 , H01L21/3144 , H01L21/76802 , Y10S438/952 , Y10S438/97
摘要： Reflection of incident optical radiation from a highly reflective metal layer (12), such as aluminum, copper or titanium, into a photoresist layer (16) is reduced by interposing a layer of silicon oxynitride (14) between the metal and photoresist layers. The silicon oxynitride layer (14) is pre-treated with an oxidizing plasma to deplete surface nitrogen and condition the silicon oxynitride layer (14) to be more compatible with deep ultraviolet photoresists. The silicon oxynitride layer (14) further serves as an etch stop in the formation of interconnect openings (40), such as vias, contacts and trenches. The interconnect opening (40) is filled with a second metallization layer to achieve multi-layer electrical interconnection.
摘要翻译：通过在金属和光致抗蚀剂层之间插入一层氮氧化硅（14），将来自诸如铝，铜或钛的高反射金属层（12）的入射光辐射反射到光致抗蚀剂层（16）中。氮氧化硅层（14）用氧化等离子体进行预处理以消除表面氮，并且使氮氧化硅层（14）与深紫外光致抗蚀剂更相容。氧氮化硅层（14）还用作形成互连开口（40）的蚀刻停止层，例如通路，触点和沟槽。互连开口（40）填充有第二金属化层以实现多层电互连。

57. 发明授权

US06270929B1 Damascene T-gate using a relacs flow 有权
标题翻译：大马士革T门使用相关资料流
公开(公告)号：US06270929B1
公开(公告)日：2001-08-07
申请号：US09619789
申请日：2000-07-20
申请人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
IPC分类号： H01L21302
CPC分类号： H01L21/28114 , H01L21/0273 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L29/42376
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. A photoresist layer is formed over the insulating layer. An opening is the formed extending through the photoresist layer and partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. The photoresist layer is swelled to reduce the size of the opening in the photoresist layer. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The opening is then filled with a conductive material to form a T-gate structure.
摘要翻译：提供了一种制造T型栅结构的方法。提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。在绝缘层上形成光致抗蚀剂层。开口形成为延伸穿过光致抗蚀剂层并部分地进入绝缘层。绝缘层中的开口从绝缘层的顶表面延伸到第一深度。光致抗蚀剂层被膨胀以减小光致抗蚀剂层中的开口的尺寸。然后将开口在绝缘层中从第一深度延伸到第二深度。开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。然后用导电材料填充开口以形成T形栅结构。

58. 发明授权

US6156658A Ultra-thin resist and silicon/oxide hard mask for metal etch 有权
标题翻译：用于金属蚀刻的超薄抗蚀剂和硅/氧化物硬掩模
公开(公告)号：US6156658A
公开(公告)日：2000-12-05
申请号：US203774
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/32136
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译：在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的硅层; 在硅层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂的厚度小于约2,000安培; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 开发暴露一部分硅层的超薄光刻胶; 蚀刻暴露出氧化物层的一部分的硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

59. 发明授权

US6143624A Shallow trench isolation formation with spacer-assisted ion implantation 有权
标题翻译：浅沟槽隔离形成与间隔子辅助离子注入
公开(公告)号：US6143624A
公开(公告)日：2000-11-07
申请号：US172088
申请日：1998-10-14
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762
CPC分类号： H01L21/76235 , H01L21/76237 , Y10S438/966 , Y10S438/981
摘要： An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
摘要翻译：通过离子注入靠近沟槽边缘的杂质形成绝缘沟槽隔离结构，以增强硅的氧化速率，并因此增加在沟槽边缘处产生的氧化物的厚度。实施例包括掩蔽和蚀刻阻挡氮化物层，在对应于随后形成的沟槽边缘的衬底的部分上形成保护性间隔物，蚀刻沟槽，去除保护性间隔物，将先前被保护隔离层覆盖的衬底的离子注入杂质，然后生长氧化物衬垫。形成在沟槽边缘上的所得氧化物由于硅氧化速率的增强而变厚，从而避免随后沉积的多晶硅层的重叠以及伴随沟槽边缘处的薄化栅极氧化物的破坏问题。

60. 发明授权

US6121123A Gate pattern formation using a BARC as a hardmask 失效
标题翻译：使用BARC作为硬掩模的栅格图案形成
公开(公告)号：US6121123A
公开(公告)日：2000-09-19
申请号：US924573
申请日：1997-09-05
申请人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
发明人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
IPC分类号： G03F7/09 , H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/3205 , H01L21/4763
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/28123 , H01L21/32139 , Y10S438/952
摘要： A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.
摘要翻译：通过使用SiON膜作为底部抗反射涂层（BARC）并随后作为硬掩模在半导体衬底上形成栅极，以更好地控制通过深UV抗蚀剂掩模定义的栅极的临界尺寸（CD）形成在其上。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层和导电层上的SiON膜。在SiON膜上形成抗蚀剂掩模。 SiON膜改善了抗蚀剂掩模形成过程，然后在随后的蚀刻工艺中用作硬掩模。然后通过依次蚀刻由原始抗蚀剂掩模中的蚀刻窗口所限定的SiON膜和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦浇口已正确成型，然后除去抗蚀剂掩模或SiON膜的任何剩余部分。

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