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1. 发明授权

US06829040B1 Lithography contrast enhancement technique by varying focus with wavelength modulation 有权
标题翻译：通过波长调制改变焦点的平版印刷对比度增强技术
公开(公告)号：US06829040B1
公开(公告)日：2004-12-07
申请号：US10703643
申请日：2003-11-07
申请人： Jongwook Kye , Ivan Lalovic , Christopher F. Lyons , Ramkumar Subramanian
发明人： Jongwook Kye , Ivan Lalovic , Christopher F. Lyons , Ramkumar Subramanian
IPC分类号： G03B2742
CPC分类号： G03F7/70575 , G03F7/703 , G03F7/70333
摘要： A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength band centered about a nominal wavelength on an optic path towards the substrate during an exposure period. A wavelength modulation system within the optic path comprises means for chromatically separating the narrow wavelength band into at least two sub-bands, the first sub-band being smaller than the narrow wavelength band and centered about a first sub-band wavelength and the second sub-band being smaller than the narrow wavelength band and centered about a second sub-band wavelength and means for passing each of the first sub-band and the second sub-band during distinct time periods within the exposure period.
摘要翻译：投影光刻系统在半导体衬底的表面上曝光感光材料，其包括高电平和低电平之间的表面高度变化。该系统包括照射源，其在曝光期间内以在光路上朝着衬底的标称波长为中心的窄波长带内投射照明。光路内的波长调制系统包括用于将窄波段色带分离成至少两个子带的装置，第一子带小于窄波段并以第一子带波长为中心，第二子带带窄于窄波长带并以第二子带波长为中心，以及用于在曝光周期内的不同时间段内通过第一子带和第二子带中的每一个的装置。

2. 发明授权

US07056804B1 Shallow trench isolation polish stop layer for reduced topography 失效
标题翻译：浅沟隔离抛光停止层减少地形
公开(公告)号：US07056804B1
公开(公告)日：2006-06-06
申请号：US10790366
申请日：2004-03-01
申请人： Christopher F. Lyons , Ramkumar Subramanian
发明人： Christopher F. Lyons , Ramkumar Subramanian
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of making and shallow trench isolation feature including 1) providing a semiconductor substrate, 2) forming a polish stop layer over the semiconductor substrate, 3) forming a nitride containing layer over the polish stop layer, 4) forming a shallow trench layer through a portion of the nitride containing layer, a portion of the polish stop layer and a portion of the semiconductor substrate, 5) removing the nitride containing layer by a chemical mechanical polishing process, and 6) planarizing the shallow trench layer and the polish stop layer until a surface of the shallow trench layer and a surface of the polish stop layer are co-planar.
摘要翻译：一种制造和浅沟槽隔离特征的方法，包括1）提供半导体衬底，2）在半导体衬底上形成抛光停止层，3）在抛光停止层上形成含氮化物层，4）形成浅沟槽层，含氮化物层的一部分，抛光停止层的一部分和半导体衬底的一部分，5）通过化学机械抛光工艺除去含氮化物层，以及6）使浅沟槽层和抛光停止层平坦化直到浅沟槽层的表面和抛光停止层的表面是共面的。

3. 发明授权

US07015504B2 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US07015504B2
公开(公告)日：2006-03-21
申请号：US10699903
申请日：2003-11-03
申请人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
发明人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
IPC分类号： H01L47/00 , H01L29/06 , H01L35/24 , H01L51/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

4. 发明授权

US07011762B1 Metal bridging monitor for etch and CMP endpoint detection 失效
标题翻译：用于蚀刻和CMP端点检测的金属桥接监视器
公开(公告)号：US07011762B1
公开(公告)日：2006-03-14
申请号：US10419534
申请日：2003-04-21
申请人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
发明人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
IPC分类号： C23F1/00 , G01R31/00
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译：本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测当它通过减色金属化过程进行时。本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动从电传感器检测和接收，用于实时监测减色金属化处理。

5. 发明授权

US06825060B1 Photosensitive polymeric memory elements 有权
标题翻译：光敏聚合物记忆元件
公开(公告)号：US06825060B1
公开(公告)日：2004-11-30
申请号：US10405272
申请日：2003-04-02
申请人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
发明人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
IPC分类号： H01L2100
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C13/04 , Y10S977/943
摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含含有光敏化合物的有机半导体层。使用图案化技术将有机半导体层形成为存储单元。

6. 发明授权

US06689541B1 Process for forming a photoresist mask 有权
标题翻译：光刻胶掩模形成工艺
公开(公告)号：US06689541B1
公开(公告)日：2004-02-10
申请号：US09884182
申请日：2001-06-19
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： G03C500
CPC分类号： G03F7/38 , G03F7/265 , G03F7/40
摘要： In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.
摘要翻译：在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。在光致抗蚀剂层中形成硅化层。硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。然后除去硅酸盐化区域，在基材上留下光刻胶掩模。

7. 发明授权

US06656763B1 Spin on polymers for organic memory devices 失效
标题翻译：旋转有机存储器件的聚合物
公开(公告)号：US06656763B1
公开(公告)日：2003-12-02
申请号：US10385375
申请日：2003-03-10
申请人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
发明人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L5140
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2213/16 , G11C2213/71 , H01L27/285 , H01L51/0003 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0084 , H01L51/0085 , Y10S977/843 , Y10S977/944
摘要： A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.
摘要翻译：公开了一种在两个电极之间制造具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。在某些溶剂的帮助下，使用旋转技术形成有机半导体层。

8. 发明授权

US06605546B1 Dual bake for BARC fill without voids 失效
标题翻译：双烘烤BARC填充无空隙
公开(公告)号：US06605546B1
公开(公告)日：2003-08-12
申请号：US09901699
申请日：2001-07-11
申请人： Ramkumar Subramanian , Wolfram Grundke , Bhanwar Singh , Christopher F. Lyons , Marina V. Plat
发明人： Ramkumar Subramanian , Wolfram Grundke , Bhanwar Singh , Christopher F. Lyons , Marina V. Plat
IPC分类号： H01L21302
CPC分类号： H01L21/76808
摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.
摘要翻译：一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。通过第一层形成至少一个孔。在至少一个孔中形成底部抗反射涂层（BARC）层。执行第一次加热以将BARC层加热至流动温度。执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。作为第二加热步骤的替代方案，BARC可以简单地硬化。第一和第二加热可以在加热室内进行，而不去除半导体衬底。

9. 发明授权

US06563221B1 Connection structures for integrated circuits and processes for their formation 失效
标题翻译：集成电路的连接结构及其形成过程
公开(公告)号：US06563221B1
公开(公告)日：2003-05-13
申请号：US10081982
申请日：2002-02-21
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L2348
CPC分类号： H01L21/76885 , H01L21/76831 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.
摘要翻译：在用于在集成电路中形成连接结构的方法中，第一导电材料沉积在衬底上并被图案化以形成与衬底的导电元件电接触的导电柱。电介质形成在衬底和导电柱上。在电介质中形成沟槽以暴露导电柱的顶部，并且第二导电材料镶嵌在沟槽中以形成与导电柱电接触的布线。衬底的导电元件可以是半导体器件或布线，接触或通孔的元件。第一导电材料可以是铝，第二导电材料可以是铜。电介质可以形成为单层，并且可以是有机低k电介质。还公开了相关的连接结构。

10. 发明授权

US06534418B1 Use of silicon containing imaging layer to define sub-resolution gate structures 有权
标题翻译：使用含硅成像层来定义次分辨率门结构
公开(公告)号：US06534418B1
公开(公告)日：2003-03-18
申请号：US09845656
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/28123 , H01L29/6659 , H01L29/7833
摘要： An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

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