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51. 发明申请

US20060212175A1 Building management system and operating method thereof 有权
标题翻译：建筑物管理系统及其操作方法
公开(公告)号：US20060212175A1
公开(公告)日：2006-09-21
申请号：US11373108
申请日：2006-03-13
申请人： Jun Kim , Sang Youn , Duck Jeon
发明人： Jun Kim , Sang Youn , Duck Jeon
IPC分类号： G01M1/38 , G05B13/00
CPC分类号： H04L12/282 , H04L12/2836 , H04L12/66 , H04L67/125 , H04L2012/285
摘要： Disclosed herein are a building management system (BMS) and an operating method thereof. A BMS controller of a LonWorks network integrally controls a multi-air conditioner system which uses a different communication scheme, without modification of the structure thereof. The building management system comprises a BMS controller (50) for centrally controlling subsystems (60 and 70) installed in the building and connected to a LonWorks network (N2), an air conditioner system (70) including a plurality of outdoor units (71) and a plurality of indoor units (72) connected to the outdoor units, and a Lon gateway (80) for converting data of an air conditioner system network (N1) into data of the LonWorks network (N2), and vice versa, to enable the BMS controller (50) to centrally control the air conditioner system (70). The building management system can incorporate a multi-air conditioner system which utilizes a different communication technology, without modification. The building management system also facilitates low-cost installation of an integrated control system in the building because each one of the indoor units constituting the multi-air conditioner system can be separately controlled without the need for a communication module to be connected to each indoor unit.
摘要翻译：这里公开了建筑物管理系统（BMS）及其操作方法。 LonWorks网络的BMS控制器整体地控制使用不同通信方案的多空调系统，而不改变其结构。建筑物管理系统包括用于集中控制安装在建筑物中并连接到LonWorks网络（N 2>）的子系统（60和70）的BMS控制器（50），空调系统（70），其包括连接到室外单元的多个室外单元（71）和多个室内单元（72），以及用于转换空调系统网络（N 1 1）的数据的Lon网关（80）变成LonWorks网络（N 2 2）的数据，反之亦然，以使得BMS控制器（50）能够集中控制空调系统（70）。建筑物管理系统可以结合使用不同通信技术的多空调系统，而无需修改。由于构成多空调系统的各个室内单元可以单独控制，而不需要将通信模块连接到每个室内单元，建筑物管理系统还有助于在建筑物中廉价安装综合控制系统。

52. 发明授权

US07039147B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07039147B2
公开(公告)日：2006-05-02
申请号：US10366865
申请日：2003-02-14
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

53. 发明申请

US20060067146A1 Integrated circuit memory system having dynamic memory bank count and page size 有权
标题翻译：具有动态存储体积和页面大小的集成电路存储器系统
公开(公告)号：US20060067146A1
公开(公告)日：2006-03-30
申请号：US10954941
申请日：2004-09-30
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器。在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

54. 发明授权

US06987823B1 System and method for aligning internal transmit and receive clocks 失效
标题翻译：用于对准内部发送和接收时钟的系统和方法
公开(公告)号：US06987823B1
公开(公告)日：2006-01-17
申请号：US09499025
申请日：2000-02-07
申请人： Donald C. Stark , Jun Kim , Stefanos Sidiropoulos
发明人： Donald C. Stark , Jun Kim , Stefanos Sidiropoulos
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G06F13/4072 , G11C7/1003 , G11C7/222 , H04L7/02
摘要： A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master. The circuit comprising a delay locked loop circuit configured to receive the first system clock and a second phase feedback signal as inputs and to generate a transmit clock signal. A 90 degrees block configured to receive the transmit system clock and to generate a 90 degrees phased shifted version of the transmit clock signal. An output driver circuit configured to receive the 90 degrees phased shifted version of the transmit clock signal and to generate the second system clock. A first phase detector configured to receive a receive system clock and the transmit system clock and to generate a first phase feedback signal. A delay element configured to receive the first system clock and the first phase feedback signal and to generate a delayed first system clock. A second phase detector configured to receive the delayed first system clock and the second system clock and to generate the second phase feedback signal.
摘要翻译：一种在系统中定义第二系统时钟的电路，包括经由信道连接到一个或多个从设备的主设备，所述通道将外部生成的第一系统时钟传送给主设备。该电路包括被配置为接收第一系统时钟和第二相位反馈信号作为输入并产生发送时钟信号的延迟锁定环电路。 90度块被配置为接收发射系统时钟并产生发射时钟信号的90度相位移位版本。输出驱动器电路，被配置为接收发射时钟信号的90度相位移位版本并产生第二系统时钟。第一相位检测器，被配置为接收接收系统时钟和发射系统时钟并产生第一相位反馈信号。延迟元件，被配置为接收第一系统时钟和第一相位反馈信号并产生延迟的第一系统时钟。第二相位检测器，被配置为接收延迟的第一系统时钟和第二系统时钟并产生第二相位反馈信号。

55. 发明申请

US20050266302A1 Secondary battery 有权
标题翻译：二次电池
公开(公告)号：US20050266302A1
公开(公告)日：2005-12-01
申请号：US11139050
申请日：2005-05-27
申请人： Jun Kim
发明人： Jun Kim
IPC分类号： H01M2/34 , H01M2/04 , H01M2/06 , H01M2/08 , H01M2/30 , H01M2/32 , H01M6/50 , H01M10/04 , H01M10/48 , H01M10/50
CPC分类号： H01M2/0456 , H01M2/0404 , H01M2/06 , H01M2/34 , H01M2/348 , H01M10/486 , H01M2200/101 , Y10T29/49108
摘要： A secondary battery having an improved electrical connection structure of a secondary protective device by positioning a thermo-breaker in a protective device groove, in order to improve the stability of the secondary battery while minimizing the occupation of the inner space of the can. The secondary battery includes an electrode assembly having positive and negative electrode tabs. A can contains the electrode assembly therein. A cap assembly has an insulated electrode terminal and a cap plate for sealing the top opening of the can. A protective device groove is formed on the bottom surface of the cap plate. A thermo-breaker is seated in the protective device groove while being connected between the first electrode tab and the electrode terminal. When the temperature inside the battery reaches a predetermined value, the bimetal loses contact and the electrical current inside the battery is interrupted, avoiding overcharge/over-discharge or explosion of the battery.
摘要翻译：一种二次电池，其具有通过将热断路器定位在保护装置槽中的二次保护装置的改进的电连接结构，以便在最小化罐的内部空间的占用的同时提高二次电池的稳定性。二次电池包括具有正极和负极接线片的电极组件。 A罐中可以包含电极组件。盖组件具有用于密封罐的顶部开口的绝缘电极端子和盖板。在盖板的底面形成保护装置槽。在第一电极接头和电极端子之间连接时，热断路器就位于保护装置槽中。当电池内部的温度达到预定值时，双金属片失去接触，并且电池内的电流被中断，从而避免电池过度充电/过度放电或爆炸。

56. 发明申请

US20050266279A1 Rechargeable battery 有权
标题翻译：可充电电池
公开(公告)号：US20050266279A1
公开(公告)日：2005-12-01
申请号：US11138319
申请日：2005-05-27
申请人： Jun Kim
发明人： Jun Kim
IPC分类号： H01M2/10 , H01M2/12 , H01M2/30 , H01M2/34 , H01M6/50 , H01M10/04 , H01M14/00
CPC分类号： H01M2/348 , H01M2/12 , H01M2/30 , H01M2/34 , H01M10/0431 , H01M2200/106
摘要： The present invention discloses a rechargeable battery that has an improved mounting structure for an electrode terminal and a second protective device used therein. This improved structure improves the function of the rechargeable battery. The rechargeable battery comprises an electrode assembly that has first electrode plate, a second electrode plate, and a separator for insulating the electrode plates from each other, all of which are wound together. It also includes a can that contains the electrode assembly therein, a cap assembly that has a cap plate for sealing a top opening of the can, an electrode terminal that is insulated and inserted into a terminal through-hole formed on the cap plate, and a terminal groove formed on the top of the terminal through-hole with a shape corresponding to that of the head of the electrode terminal so that the head of the electrode terminal can be housed therein. The rechargeable battery of the present invention also includes a protective device groove spaced at a predetermined distance from the terminal groove and a second protective device housed in the protective device groove with one end connected to the top surface of the electrode terminal.
摘要翻译：本发明公开了一种可充电电池，其具有用于电极端子的改进的安装结构和其中使用的第二保护装置。这种改进的结构改善了可再充电电池的功能。可充电电池包括具有第一电极板，第二电极板和用于将电极板彼此绝缘的隔板的电极组件，所有这些都被卷绕在一起。它还包括其中包含电极组件的罐，盖组件，其具有用于密封罐的顶部开口的盖板，绝缘并插入形成在盖板上的端子通孔中的电极端子，以及形成在端子通孔的顶部上的端子槽，其形状与电极端子的头部的形状相对应，使得电极端子的头部可以容纳在其中。本发明的可再充电电池还包括与端子槽隔开预定距离的保护装置槽和容纳在保护装置槽中的第二保护装置，其一端连接到电极端子的顶表面。

57. 发明申请

US20050220235A1 System and method for aligning internal transmit and receive clocks 审中-公开
标题翻译：用于对准内部发送和接收时钟的系统和方法
公开(公告)号：US20050220235A1
公开(公告)日：2005-10-06
申请号：US11130506
申请日：2005-05-16
申请人： Donald Stark , Jun Kim , Stefanos Sidiropoulos
发明人： Donald Stark , Jun Kim , Stefanos Sidiropoulos
IPC分类号： H04J3/06 , H04L7/00 , H04L7/02
CPC分类号： H04L7/0008 , G06F13/4072 , G11C7/1003 , G11C7/222 , H04L7/02
摘要： A system includes a master device connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master device. A delay locked loop circuit receives the first system clock and a second phase feedback signal as inputs and generates a transmit clock signal. A phase offset circuit receives the transmit system clock and generates a phase shifted version of the transmit clock signal as a second system clock. A first phase detector receives a receive system clock and the transmit system clock and generates a first phase feedback signal. A delay element receives the first system clock and the first phase feedback signal and generates a delayed first system clock. A second phase detector receives the delayed first system clock and the second system clock and generates the second phase feedback signal.
摘要翻译：系统包括经由信道连接到一个或多个从设备的主设备，该信道将外部产生的第一系统时钟传送到主设备。延迟锁定环电路接收第一系统时钟和第二相位反馈信号作为输入，并产生发送时钟信号。相位偏移电路接收发射系统时钟并产生作为第二系统时钟的发送时钟信号的相移版本。第一相位检测器接收接收系统时钟和发射系统时钟并产生第一相位反馈信号。延迟元件接收第一系统时钟和第一相位反馈信号并产生延迟的第一系统时钟。第二相位检测器接收延迟的第一系统时钟和第二系统时钟并产生第二相位反馈信号。

58. 发明申请

US20050181272A1 Lithium ion secondary battery 失效
标题翻译：锂离子二次电池
公开(公告)号：US20050181272A1
公开(公告)日：2005-08-18
申请号：US10965734
申请日：2004-10-18
申请人： Jun Kim
发明人： Jun Kim
IPC分类号： H01M2/02 , H01M2/04 , H01M2/08 , H01M2/12 , H01M2/36 , H01M10/05 , H01M10/0525 , H01M10/0566 , H01M10/0587
CPC分类号： H01M2/1241 , H01M2/0202 , H01M2/36 , H01M10/0525 , H01M10/0587
摘要： A lithium ion secondary battery in which a safety vent as a safety device for a swelling phenomenon functions under a low pressure. A notch is formed in an inner surface of a large-area wall of the secondary battery, and an auxiliary notch is formed in an outer surface to correspond to the notch formed in the inner surface.
摘要翻译：其中作为膨胀现象的安全装置的安全排气口在低压下起作用的锂离子二次电池。在二次电池的大面积壁的内表面上形成有凹口，并且在外表面上形成辅助凹口以对应于形成在内表面中的凹口。

59. 发明授权

US06922092B2 Impedance controlled output driver 失效
标题翻译：阻抗控制输出驱动
公开(公告)号：US06922092B2
公开(公告)日：2005-07-26
申请号：US10731718
申请日：2003-12-08
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003 , H03K5/12
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译：输出驱动器具有输出多路复用器和输出电流驱动器。输出多路复用器接收数据信号并输出q-节点信号。输出电流驱动器接收q-节点信号并根据q-节点信号驱动总线。输出多路复用器以各种方式处理数据信号以产生q-结点信号。输出电流驱动器响应于当前控制位以选择输出驱动电流的量。此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

60. 发明申请

US20050081240A1 Digital broadcasting receiver and method for displaying service component of digital broadcasting 审中-公开
标题翻译：数字广播接收机及显示数字广播服务组件的方法
公开(公告)号：US20050081240A1
公开(公告)日：2005-04-14
申请号：US10954818
申请日：2004-09-29
申请人： Jun Kim , Sang Park
发明人： Jun Kim , Sang Park
IPC分类号： G06F13/00 , H04B1/06 , H04H40/18 , H04N5/44 , H04N5/445 , H04N7/08
CPC分类号： H04H40/18
摘要： Provided are a method for effectively displaying a service component of a digital broadcasting and a digital broadcasting receiver that allow a user to effectively to select a desired service component by displaying the service component contained in one ensemble according to a characteristic of the service component.
摘要翻译：提供了一种用于有效地显示数字广播的服务组件和数字广播接收机的方法，其允许用户根据服务组件的特征显示包含在一个集合中的服务组件来有效地选择所需的服务组件。

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