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1. 发明授权

US06922092B2 Impedance controlled output driver 失效
标题翻译：阻抗控制输出驱动
公开(公告)号：US06922092B2
公开(公告)日：2005-07-26
申请号：US10731718
申请日：2003-12-08
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003 , H03K5/12
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译：输出驱动器具有输出多路复用器和输出电流驱动器。输出多路复用器接收数据信号并输出q-节点信号。输出电流驱动器接收q-节点信号并根据q-节点信号驱动总线。输出多路复用器以各种方式处理数据信号以产生q-结点信号。输出电流驱动器响应于当前控制位以选择输出驱动电流的量。此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

2. 发明授权

US06342800B1 Charge compensation control circuit and method for use with output driver 失效
标题翻译：充电补偿控制电路及其与输出驱动器的配合使用
公开(公告)号：US06342800B1
公开(公告)日：2002-01-29
申请号：US09698997
申请日：2000-10-26
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： H03K512
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译：输出驱动器具有输出多路复用器和输出电流驱动器。输出多路复用器接收数据信号并输出q-节点信号。输出电流驱动器接收q-节点信号并根据q-节点信号驱动总线。输出多路复用器以各种方式处理数据信号以产生q-结点信号。输出电流驱动器响应于当前控制位以选择输出驱动电流的量。此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

3. 发明授权

US07755968B2 Integrated circuit memory device having dynamic memory bank count and page size 有权
标题翻译：集成电路存储器件，具有动态存储体积计数和页面大小
公开(公告)号：US07755968B2
公开(公告)日：2010-07-13
申请号：US11834915
申请日：2007-08-07
申请人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.
摘要翻译：集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸第二种操作模式。存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

4. 发明授权

US6163178A Impedance controlled output driver 有权
标题翻译：阻抗控制输出驱动
公开(公告)号：US6163178A
公开(公告)日：2000-12-19
申请号：US222590
申请日：1998-12-28
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译：输出驱动器具有输出多路复用器和输出电流驱动器。输出多路复用器接收数据信号并输出q-节点信号。输出电流驱动器接收q-节点信号并根据q-节点信号驱动总线。输出多路复用器以各种方式处理数据信号以产生q-结点信号。输出电流驱动器响应于当前控制位以选择输出驱动电流的量。此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

5. 发明授权

US07274244B2 Pulse multiplexed output system 有权
标题翻译：脉冲多路复用输出系统
公开(公告)号：US07274244B2
公开(公告)日：2007-09-25
申请号：US11123225
申请日：2005-05-06
申请人： Wayne Fang , Wayne S. Richardson , Kurt T. Knorpp
发明人： Wayne Fang , Wayne S. Richardson , Kurt T. Knorpp
IPC分类号： H03K17/00
CPC分类号： H03K17/693
摘要： A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.
摘要翻译：公开了脉冲多路复用输出子系统。在一个特定示例性实施例中，输出子系统可以包括多个脉冲发生器，第一对晶体管和第二对晶体管，其中第一对晶体管中的每一个耦合到第一对晶体管中的相应一个多个脉冲发生器，并且其中第二对晶体管中的每一个耦合到第二对多个脉冲发生器中的相应一个。输出子系统还可以包括第一对电阻负载，其中第一对电阻负载中的每一个耦合到第一对晶体管中的相应一个和第二对晶体管中的相应一个，以及第一电流源耦合到第一对晶体管和第二对晶体管。

6. 发明授权

US07254075B2 Integrated circuit memory system having dynamic memory bank count and page size 有权
标题翻译：具有动态存储体积和页面大小的集成电路存储器系统
公开(公告)号：US07254075B2
公开(公告)日：2007-08-07
申请号：US10954941
申请日：2004-09-30
申请人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad A. Bellows , Wayne S. Richardson , Kurt T. Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。在第二操作模式期间，第二多个数据从第一行存储单元传送到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器。在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

7. 发明授权

US07091761B2 Impedance controlled output driver 有权
标题翻译：阻抗控制输出驱动
公开(公告)号：US07091761B2
公开(公告)日：2006-08-15
申请号：US11148783
申请日：2005-06-08
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： H03K5/12
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译：输出驱动器具有输出多路复用器和输出电流驱动器。输出多路复用器接收数据信号并输出q-节点信号。输出电流5河接收q节点信号，并根据q-节点信号驱动总线。输出多路复用器以各种方式处理数据信号以产生q-结点信号。输出电流驱动器响应于当前控制位以选择输出驱动电流的量。此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

8. 发明授权

US06661268B2 Charge compensation control circuit and method for use with output driver 失效
公开(公告)号：US06661268B2
公开(公告)日：2003-12-09
申请号：US10014650
申请日：2001-12-11
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： H03K512
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

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