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1. 发明授权

US08630317B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08630317B2
公开(公告)日：2014-01-14
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

2. 发明授权

US08305839B2 Memory device having multiple power modes 有权
标题翻译：具有多种功率模式的存储器件
公开(公告)号：US08305839B2
公开(公告)日：2012-11-06
申请号：US13352177
申请日：2012-01-17
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。数据接口与第一个接口分开。第二个接口与第一个接口和数据接口分开。存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。

3. 发明授权

US08205056B2 Memory controller for controlling write signaling 有权
标题翻译：用于控制写入信号的存储器控制器
公开(公告)号：US08205056B2
公开(公告)日：2012-06-19
申请号：US13230741
申请日：2011-09-12
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.
摘要翻译：存储器控制器具有在第一组互连资源上传送指定激活一行存储器单元的第一命令的接口，指定针对存储器单元行的写操作的第二命令，指定是否与写入操作相关地进行预充电，指定是否将与写入操作相关联地发布数据掩码信息的代码，以及如果代码指定将发出数据掩码信息的数据掩码信息，指定是否选择性地写入与写入操作相关联的写入数据的部分。存储器控制器接口还通过第二组互连资源与第一组互连资源（写入数据）分离。

4. 发明申请

US20120113738A1 Memory Device Having Multiple Power Modes 有权
公开(公告)号：US20120113738A1
公开(公告)日：2012-05-10
申请号：US13352177
申请日：2012-01-17
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampe , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampe , Donald C. Stark
IPC分类号： G11C5/14
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

5. 发明申请

US20110090755A1 Memory Device Having Multiple Power Modes 有权
标题翻译：具有多种功率模式的存储器件
公开(公告)号：US20110090755A1
公开(公告)日：2011-04-21
申请号：US12975322
申请日：2010-12-21
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。数据接口与第一个接口分开。第二个接口与第一个接口和数据接口分开。存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。

6. 发明申请

US20100146321A1 SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM 有权
标题翻译：单时钟，无连字信号系统
公开(公告)号：US20100146321A1
公开(公告)日：2010-06-10
申请号：US12706662
申请日：2010-02-16
申请人： Donald C. STARK
发明人： Donald C. STARK
IPC分类号： G06F1/08
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
摘要翻译：信令系统包括信令路径，耦合到信令路径的主设备，耦合到信令路径的从设备和时钟发生器。从设备包括定时电路，用于产生具有相对于由时钟发生器提供的时钟信号的相位偏移的内部时钟信号，相位偏移至少部分地由信号路径上的信号传播时间确定。

7. 发明申请

US20100046314A1 Memory Device Having a Read Pipeline and a Delay Locked Loop 有权
标题翻译：具有读取流水线和延迟锁定环路的存储器件
公开(公告)号：US20100046314A1
公开(公告)日：2010-02-25
申请号：US12608209
申请日：2009-10-29
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。时钟接收器电路接收外部时钟信号。控制接口接收指定对存储器件的读取操作的命令。数据接口在存储器件和外部信号线组之间传送数据。延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。读取管线电路将从存储器核心访问的读取数据提供给数据接口。响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。

8. 发明申请

US20090129178A1 Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time 有权
标题翻译：具有基于读响应时间的延迟写时序的集成电路存储器件
公开(公告)号：US20090129178A1
公开(公告)日：2009-05-21
申请号：US12349485
申请日：2009-01-06
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G11C11/416
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
摘要翻译：集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

9. 发明申请

US20080267000A1 SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM 失效
标题翻译：单时钟，无连字信号系统
公开(公告)号：US20080267000A1
公开(公告)日：2008-10-30
申请号：US12166248
申请日：2008-07-01
申请人： Donald C. STARK
发明人： Donald C. STARK
IPC分类号： G11C8/18
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
摘要翻译：信令系统包括信令路径，耦合到信令路径的主设备，耦合到信令路径的从设备和时钟发生器。从设备包括定时电路，用于产生具有相对于由时钟发生器提供的时钟信号的相位偏移的内部时钟信号，相位偏移至少部分地由信号路径上的信号传播时间确定。

10. 发明申请

US20080162759A1 METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS MEMORY SYSTEM 有权
标题翻译：调整同步存储器系统性能的方法和装置
公开(公告)号：US20080162759A1
公开(公告)日：2008-07-03
申请号：US12036598
申请日：2008-02-25
申请人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
发明人： Bruno Werner Garlepp , Pak Shing Chau , Kevin S. Donnelly , Clemenz Portmann , Donald C. Stark , Stefanos Sidiropoulos , Richard M. Barth , Paul G. Davis , Ely K. Tsern
IPC分类号： G06F13/18
CPC分类号： G11C7/1048 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
摘要翻译：提供了一种用于调整存储器系统的性能的方法和装置。存储器系统包括主设备和从设备。存储器通道将主设备耦合到从设备，使得从设备经由存储器通道从主设备接收系统操作信息。从设备还包括用于在从设备内调谐电路的装置，从而提高存储器系统的性能。

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