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1. 发明申请

US20050220235A1 System and method for aligning internal transmit and receive clocks 审中-公开
标题翻译：用于对准内部发送和接收时钟的系统和方法
公开(公告)号：US20050220235A1
公开(公告)日：2005-10-06
申请号：US11130506
申请日：2005-05-16
申请人： Donald Stark , Jun Kim , Stefanos Sidiropoulos
发明人： Donald Stark , Jun Kim , Stefanos Sidiropoulos
IPC分类号： H04J3/06 , H04L7/00 , H04L7/02
CPC分类号： H04L7/0008 , G06F13/4072 , G11C7/1003 , G11C7/222 , H04L7/02
摘要： A system includes a master device connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master device. A delay locked loop circuit receives the first system clock and a second phase feedback signal as inputs and generates a transmit clock signal. A phase offset circuit receives the transmit system clock and generates a phase shifted version of the transmit clock signal as a second system clock. A first phase detector receives a receive system clock and the transmit system clock and generates a first phase feedback signal. A delay element receives the first system clock and the first phase feedback signal and generates a delayed first system clock. A second phase detector receives the delayed first system clock and the second system clock and generates the second phase feedback signal.
摘要翻译：系统包括经由信道连接到一个或多个从设备的主设备，该信道将外部产生的第一系统时钟传送到主设备。延迟锁定环电路接收第一系统时钟和第二相位反馈信号作为输入，并产生发送时钟信号。相位偏移电路接收发射系统时钟并产生作为第二系统时钟的发送时钟信号的相移版本。第一相位检测器接收接收系统时钟和发射系统时钟并产生第一相位反馈信号。延迟元件接收第一系统时钟和第一相位反馈信号并产生延迟的第一系统时钟。第二相位检测器接收延迟的第一系统时钟和第二系统时钟并产生第二相位反馈信号。

2. 发明申请

US20060120409A1 Calibrated data communication system and method 有权
公开(公告)号：US20060120409A1
公开(公告)日：2006-06-08
申请号：US11327213
申请日：2006-01-05
申请人： Jared Zerbe , Kevin Donnelly , Stefanos Sidiropoulos , Donald Stark , Mark Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno Garlepp , Tsyr-Chyang Ho , Benedict Lau
发明人： Jared Zerbe , Kevin Donnelly , Stefanos Sidiropoulos , Donald Stark , Mark Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno Garlepp , Tsyr-Chyang Ho , Benedict Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

3. 发明授权

US06950956B2 Integrated circuit with timing adjustment mechanism and method 有权
标题翻译：具有定时调整机制和方法的集成电路
公开(公告)号：US06950956B2
公开(公告)日：2005-09-27
申请号：US10700655
申请日：2003-11-03
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F1/10 , G06F13/42 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.
摘要翻译：集成电路装置包括接收器，寄存器和时钟电路。接收机响应于内部时钟信号从外部信号线采样数据。寄存器存储一个表示定时偏移量的值，以调整数据采样的时间。时钟电路产生内部时钟信号，使得内部时钟信号相对于外部时钟信号保持受控的定时关系。时钟电路包括内插器，其相位混合一组参考时钟信号，使得内部时钟信号根据该值相位偏移。

4. 发明授权

US07535933B2 Calibrated data communication system and method 有权
标题翻译：校准数据通信系统及方法
公开(公告)号：US07535933B2
公开(公告)日：2009-05-19
申请号：US11327213
申请日：2006-01-05
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

5. 发明授权

US08630317B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08630317B2
公开(公告)日：2014-01-14
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

6. 发明授权

US06987823B1 System and method for aligning internal transmit and receive clocks 失效
标题翻译：用于对准内部发送和接收时钟的系统和方法
公开(公告)号：US06987823B1
公开(公告)日：2006-01-17
申请号：US09499025
申请日：2000-02-07
申请人： Donald C. Stark , Jun Kim , Stefanos Sidiropoulos
发明人： Donald C. Stark , Jun Kim , Stefanos Sidiropoulos
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G06F13/4072 , G11C7/1003 , G11C7/222 , H04L7/02
摘要： A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master. The circuit comprising a delay locked loop circuit configured to receive the first system clock and a second phase feedback signal as inputs and to generate a transmit clock signal. A 90 degrees block configured to receive the transmit system clock and to generate a 90 degrees phased shifted version of the transmit clock signal. An output driver circuit configured to receive the 90 degrees phased shifted version of the transmit clock signal and to generate the second system clock. A first phase detector configured to receive a receive system clock and the transmit system clock and to generate a first phase feedback signal. A delay element configured to receive the first system clock and the first phase feedback signal and to generate a delayed first system clock. A second phase detector configured to receive the delayed first system clock and the second system clock and to generate the second phase feedback signal.
摘要翻译：一种在系统中定义第二系统时钟的电路，包括经由信道连接到一个或多个从设备的主设备，所述通道将外部生成的第一系统时钟传送给主设备。该电路包括被配置为接收第一系统时钟和第二相位反馈信号作为输入并产生发送时钟信号的延迟锁定环电路。 90度块被配置为接收发射系统时钟并产生发射时钟信号的90度相位移位版本。输出驱动器电路，被配置为接收发射时钟信号的90度相位移位版本并产生第二系统时钟。第一相位检测器，被配置为接收接收系统时钟和发射系统时钟并产生第一相位反馈信号。延迟元件，被配置为接收第一系统时钟和第一相位反馈信号并产生延迟的第一系统时钟。第二相位检测器，被配置为接收延迟的第一系统时钟和第二系统时钟并产生第二相位反馈信号。

7. 发明申请

US20120204054A1 Memory System with Calibrated Data Communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US20120204054A1
公开(公告)日：2012-08-09
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

8. 发明申请

US20090327789A1 Memory System with Calibrated Data Communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US20090327789A1
公开(公告)日：2009-12-31
申请号：US12430836
申请日：2009-04-27
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： G06F11/00 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

9. 发明授权

US08170067B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08170067B2
公开(公告)日：2012-05-01
申请号：US12430836
申请日：2009-04-27
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

10. 发明授权

US07042914B2 Calibrated data communication system and method 失效
公开(公告)号：US07042914B2
公开(公告)日：2006-05-09
申请号：US10684618
申请日：2003-10-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

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