专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20080101145A1 Method Of Providing Optimal Field Programming Of Electronic Fuses 失效
标题翻译：提供电子保险丝最优现场编程的方法
公开(公告)号：US20080101145A1
公开(公告)日：2008-05-01
申请号：US11555323
申请日：2006-11-01
申请人： Troy J. Perry , Michael R. Ouellette
发明人： Troy J. Perry , Michael R. Ouellette
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/02 , G11C29/021 , G11C29/027 , G11C29/028 , G11C2029/5006
摘要： A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable fashion on the customer's IC chip. Accessing the optimal fuse programming identifier on the customer's IC chip, the customer may apply a fuse programming process in the field according to one or more correlated optimal fuse programming conditions.
摘要翻译：一种提供最佳熔丝编程条件的方法，集成电路芯片客户可以通过该条件来编程现场的电子熔丝，即在制造测试环境之外。可以以客户的IC芯片的可读方式向客户提供与最佳熔丝编程条件相关的最佳熔丝编程标识符。访问客户IC芯片上的最佳熔丝编程标识符，客户可以根据一个或多个相关的最佳熔丝编程条件在现场应用熔丝编程过程。

52. 发明申请

US20080002451A1 SYSTEM AND METHOD FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：没有参考熔丝的差分EFUSE感应系统和方法
公开(公告)号：US20080002451A1
公开(公告)日：2008-01-03
申请号：US11427849
申请日：2006-06-30
申请人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
发明人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器电压。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

53. 发明授权

US07304901B2 Enabling memory redundancy during testing 有权
标题翻译：在测试期间启用内存冗余
公开(公告)号：US07304901B2
公开(公告)日：2007-12-04
申请号：US11160268
申请日：2005-06-16
申请人： Michael R. Ouellette , Jeremy Rowland
发明人： Michael R. Ouellette , Jeremy Rowland
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.
摘要翻译：用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。冗余存储器元件（20）仅在使能时被测试。

54. 发明授权

US06961276B2 Random access memory having an adaptable latency 失效
公开(公告)号：US06961276B2
公开(公告)日：2005-11-01
申请号：US10664789
申请日：2003-09-17
申请人： Francois Ibrahim Atallah , James Norris Dieffenderfer , Jeffrey H. Fischer , Michael Thomas Fragano , Daniel Stephen Geise , Jeffery Howard Oppold , Michael R. Ouellette , Neelesh Govindaraya Pai , William Robert Reohr , Joel Abraham Silberman , Thomas Philip Speier
发明人： Francois Ibrahim Atallah , James Norris Dieffenderfer , Jeffrey H. Fischer , Michael Thomas Fragano , Daniel Stephen Geise , Jeffery Howard Oppold , Michael R. Ouellette , Neelesh Govindaraya Pai , William Robert Reohr , Joel Abraham Silberman , Thomas Philip Speier
IPC分类号： G11C7/02 , G11C7/06 , G11C7/10 , G11C7/22 , G11C11/22
CPC分类号： G11C7/22 , G11C7/06 , G11C7/1045
摘要： A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.

55. 发明授权

US06928377B2 Self-test architecture to implement data column redundancy in a RAM 有权
公开(公告)号：US06928377B2
公开(公告)日：2005-08-09
申请号：US10658940
申请日：2003-09-09
申请人： Steven M. Eustis , Krishnendu Mondal , Michael R. Ouellette , Jeremy P. Rowland
发明人： Steven M. Eustis , Krishnendu Mondal , Michael R. Ouellette , Jeremy P. Rowland
IPC分类号： G01R31/28 , G01R31/00 , G06F19/00 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.

56. 发明授权

US06552920B2 Saving content addressable memory power through conditional comparisons 有权
标题翻译：通过条件比较保存内容可寻址的内存电源
公开(公告)号：US06552920B2
公开(公告)日：2003-04-22
申请号：US09892396
申请日：2001-06-27
申请人： Thomas B. Chadwick , Tarl S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Ouellette
发明人： Thomas B. Chadwick , Tarl S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Ouellette
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译：用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。

57. 发明授权

US5912901A Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure 失效
标题翻译：用于测试集成电路的方法和内置自检装置，其捕获所选故障的故障信息
公开(公告)号：US5912901A
公开(公告)日：1999-06-15
申请号：US823446
申请日：1997-03-24
申请人： R. Dean Adams , Michael R. Ouellette , Ronald J. Prilik
发明人： R. Dean Adams , Michael R. Ouellette , Ronald J. Prilik
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G06F11/22 , G11C29/12
CPC分类号： G01R31/318555 , G01R31/2884 , G01R31/319
摘要： A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.
摘要翻译：公开了一种用于测试集成电路的内置自检（BIST）装置和方法，其能够捕获所选故障的故障数据。 BIST装置包括产生至少第一时钟信号的时钟发生器和内置自测试器，其响应于第一时钟信号将预定的输入数据模式应用于集成电路。此外，BIST装置包括用于将从集成电路接收的输出数据与预期输出数据进行比较的数据比较器。当从集成电路接收的输出数据与预期输出数据不同时，数据比较器检测集成电路内的故障。 BIST装置还包括时钟控制器，其响应于所选择的故障发生的检测而禁用第一时钟信号。通过在所选择的故障发生时能够对要停止的集成电路进行测试，增强了集成电路的故障分析。

58. 发明授权

US08839054B2 Read only memory (ROM) with redundancy 有权
标题翻译：只读存储器（ROM）冗余
公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译：提供了具有冗余性和使用方法的只读存储器（ROM）。具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。

59. 发明授权

US08656325B2 Integrated circuit design method and system 有权
标题翻译：集成电路设计方法与系统
公开(公告)号：US08656325B2
公开(公告)日：2014-02-18
申请号：US13348850
申请日：2012-01-12
申请人： John E. Barwin , Amol A. Joshi , Baozhen Li , Michael R. Ouellette
发明人： John E. Barwin , Amol A. Joshi , Baozhen Li , Michael R. Ouellette
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/76 , G06F2217/78
摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.
摘要翻译：公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。为了建立设计约束的目的，对短和长金属部件进行不同的处理。对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者，用作该短金属部件的设计约束。对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。

60. 发明授权

US08537627B2 Determining fusebay storage element usage 有权
标题翻译：确定保险丝存储元件的使用情况
公开(公告)号：US08537627B2
公开(公告)日：2013-09-17
申请号：US13223949
申请日：2011-09-01
申请人： Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C7/00
CPC分类号： G11C29/787 , G11C29/4401 , G11C2029/4402
摘要： Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.
摘要翻译：对所使用的熔断器存储元件进行计数，使得数据的存储可以在第一未使用的存储元件开始。修理寄存器长度和许多以前的通行存储在保险丝盒的保险丝插头中。当一些数据被发送到修复寄存器时，修复寄存器位置跟踪器值将被改变一到达到第一个值。当达到第一个值时，通过跟踪器值改变一。如果没有达到第一个值，则重复这些步骤。可以包括位计数器和/或页计数器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式