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1. 发明授权

US08719648B2 Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture 失效
标题翻译：在单个保险丝架构中交织内存修复数据压缩和保险丝编程操作
公开(公告)号：US08719648B2
公开(公告)日：2014-05-06
申请号：US13192051
申请日：2011-07-27
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译：描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。

2. 发明申请

US20130058176A1 DETERMINING FUSEBAY STORAGE ELEMENT USAGE 有权
标题翻译：确定FUSEBAY存储元件使用
公开(公告)号：US20130058176A1
公开(公告)日：2013-03-07
申请号：US13223949
申请日：2011-09-01
申请人： Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/04
CPC分类号： G11C29/787 , G11C29/4401 , G11C2029/4402
摘要： Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.
摘要翻译：对所使用的熔断器存储元件进行计数，使得数据的存储可以在第一未使用的存储元件开始。修理寄存器长度和许多以前的通行存储在保险丝盒的保险丝插头中。当一些数据被发送到修复寄存器时，修复寄存器位置跟踪器值将被改变一到达到第一个值。当达到第一个值时，通过跟踪器值改变一。如果没有达到第一个值，则重复这些步骤。可以包括位计数器和/或页计数器。

3. 发明申请

US20130031319A1 INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING OPERATIONS IN SINGLE FUSEBAY ARCHITECTURE 失效
标题翻译：记忆体修复数据压缩和单个保险丝架构中的保险丝编程操作
公开(公告)号：US20130031319A1
公开(公告)日：2013-01-31
申请号：US13192051
申请日：2011-07-27
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G06F12/06
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译：描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。

4. 发明申请

US20090099828A1 Device Threshold Calibration Through State Dependent Burnin 审中-公开
标题翻译：通过状态依赖的Burnin设备阈值校准
公开(公告)号：US20090099828A1
公开(公告)日：2009-04-16
申请号：US11871198
申请日：2007-10-12
申请人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
发明人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
IPC分类号： G06F17/50 , G01R31/317
CPC分类号： G11C29/02 , G11C11/41 , G11C29/026 , G11C29/06 , G11C29/50 , G11C2029/5004
摘要： Disclosed are embodiments of a design structure for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.
摘要翻译：公开了用于减少和/或消除失配的设计结构的实施例。这些实施例在芯片烧录之前对需要平衡状态的一个或多个电路子部件（例如，在每个存储器单元中的交叉耦合晶体管的偏置和/或存储器阵列中的读出放大器）进行采样，通过启动老化过程，在该过程中，单独选择的状态被应用于电路中的每个设备。这使得设备远离其优选的状态并且朝向平衡状态。在老化过程中定期重新评估偏差，以避免过度校正。通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。

5. 发明授权

US08467260B2 Structure and method for storing multiple repair pass data into a fusebay 有权
标题翻译：用于将多个修复传递数据存储到保险丝盒中的结构和方法
公开(公告)号：US08467260B2
公开(公告)日：2013-06-18
申请号：US13198894
申请日：2011-08-05
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译：相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。

6. 发明授权

US08214699B2 Circuit structure and method for digital integrated circuit performance screening 有权
标题翻译：数字集成电路性能筛选的电路结构及方法
公开(公告)号：US08214699B2
公开(公告)日：2012-07-03
申请号：US12147670
申请日：2008-06-27
申请人： Igor Arsovski , David J. Wager , Michael A. Ziegerhofer
发明人： Igor Arsovski , David J. Wager , Michael A. Ziegerhofer
IPC分类号： G11C29/12
CPC分类号： G06F13/4243
摘要： Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met.
摘要翻译：公开了具有数字集成电路的半导体芯片，例如存储器件（例如，静态随机存取存储器（SRAM）阵列，动态随机存取存储器（DRAM）阵列，内容可寻址存储器（CAM）阵列等）），其可以选择性地在功能模式或性能筛选模式下操作。在功能模式中，使用由外部信号发生器提供的第一信号来激活电路中的第一设备，并且作为响应，电路中的第二设备输出数据输出信号。在演奏屏蔽模式中，第二信号由内部信号发生器基于数据输出信号内部产生。然后该第二信号用于激活电路中的第一设备，并且作为响应，第二设备输出数据输出信号。因此，在性能筛选模式下，数字集成电路被有效地转换为性能屏幕环形振荡器（PSRO），其输出可以被监视以确定是否满足数字集成电路的性能标准。

7. 发明授权

US07826288B2 Device threshold calibration through state dependent burn-in 有权
标题翻译：通过状态相关的老化进行设备阈值校准
公开(公告)号：US07826288B2
公开(公告)日：2010-11-02
申请号：US11684225
申请日：2007-03-09
申请人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
发明人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
IPC分类号： G11C29/00 , G11C7/06 , G11C11/413 , G11C29/50 , G11C29/06 , G11C11/412
CPC分类号： G11C29/50 , G11C11/41 , G11C29/028
摘要： In a method for reducing and/or eliminating mismatch in one or more devices that require a balanced state (e.g., in cross-coupled transistors in each memory cell and/or sense amp in a memory array), the bias (i.e., the preferred state) of each of the devices is determined. Then, a burn-in process is initiated, during which an individually selected state is applied to each of the devices. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.
摘要翻译：在用于减少和/或消除需要平衡状态的一个或多个器件（例如，在每个存储器单元中的交叉耦合晶体管和/或存储器阵列中的读出放大器）中的失配的方法中，偏差（即，优选的状态）被确定。然后，启动老化过程，在此期间，将单独选择的状态应用于每个设备。这使得设备远离其优选的状态并且朝向平衡状态。在老化过程中定期重新评估偏差，以避免过度校正。通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。

8. 发明授权

US08595678B2 Validating interconnections between logic blocks in a circuit description 失效
标题翻译：验证电路描述中的逻辑块之间的互连
公开(公告)号：US08595678B2
公开(公告)日：2013-11-26
申请号：US13365370
申请日：2012-02-03
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译：公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接块和其他逻辑块。

9. 发明申请

US20130205268A1 VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION 失效
标题翻译：验证电路中逻辑块之间的互连
公开(公告)号：US20130205268A1
公开(公告)日：2013-08-08
申请号：US13365370
申请日：2012-02-03
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译：公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接块和其他逻辑块。

10. 发明申请

US20130042166A1 FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD 有权
标题翻译： FUSEBAY控制器结构，系统和方法
公开(公告)号：US20130042166A1
公开(公告)日：2013-02-14
申请号：US13204929
申请日：2011-08-08
申请人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译：选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。每个状态机可以包括当遇到其类型的校正时可以被激活的指示器，例如粘性位。指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。

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