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    • 51. 发明申请
      US20050153502A1 Flash memory device and method of manufacturing the same 有权
    • Flash memory device and method of manufacturing the same
    • 闪存装置及其制造方法
    • US20050153502A1
    • 2005-07-14
    • US11025279
    • 2004-12-29
    • Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
    • Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
    • H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
    • H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328
    • A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
    • 提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。 通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。 选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。 栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。 具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。 通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。 使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 56. 发明授权
      US07256448B2 Split gate type nonvolatile semiconductor memory device, and method of fabricating the same 失效
    • Split gate type nonvolatile semiconductor memory device, and method of fabricating the same
    • 分路型非易失性半导体存储器件及其制造方法
    • US07256448B2
    • 2007-08-14
    • US11349402
    • 2006-02-07
    • Heeseog Jeon , Seung-beom Yoon , Yong-tae Kim , Yong-suk Choi
    • Heeseog Jeon , Seung-beom Yoon , Yong-tae Kim , Yong-suk Choi
    • H01L29/788
    • H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
    • A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.
    • 提供一种分离栅极型非易失性半导体存储器件及其制造分离栅型非易失性半导体存储器件的方法。 在半导体衬底上形成栅绝缘层和浮栅导电层。 掩模层图案形成在浮栅导电层上以限定沿第一方向延伸的第一开口。 具有预定宽度的第一牺牲间隔物形成在对应于掩模层图案的两个侧壁上。 栅极间绝缘层形成在浮栅导电层上。 去除第一牺牲间隔物，并且蚀刻浮栅导电层，直到露出栅极绝缘层。 隧道绝缘层形成在浮栅导电层的露出部分上。 在半导体衬底的表面上形成控制栅导电层。 在控制栅极导电层上形成具有预定宽度的第二牺牲间隔物。 通过蚀刻暴露的控制栅极导电层，在第一开口中形成分裂控制栅极。 蚀刻剩余的掩模层图案和栅极间绝缘层，直到浮栅导电层露出。 蚀刻暴露的浮栅导电层，以在第一开口中形成分离浮栅。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 57. 发明授权
      US07037781B2 Local SONOS-type nonvolatile memory device and method of manufacturing the same 失效
    • Local SONOS-type nonvolatile memory device and method of manufacturing the same
    • 本地SONOS型非易失性存储器件及其制造方法
    • US07037781B2
    • 2006-05-02
    • US10888660
    • 2004-07-09
    • Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim
    • Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim
    • H01L21/336
    • H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/66833 , H01L29/792
    • Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.
    • 提供本地SONOS型存储器件及其制造方法。 该器件包括形成在硅衬底上的栅氧化层; 导电间隔物和虚拟间隔物，其形成在栅极氧化物层上并彼此分离，导电间隔物和虚设间隔物具有面向外的圆形表面; 形成在所述导电间隔物的侧壁上的一对绝缘间隔件和所述虚拟间隔件的彼此面对的侧壁; 在所述一对绝缘间隔物之间​​以自对准的方式形成的ONO层; 在所述一对绝缘间隔物之间​​以自对准的方式在所述ONO层上形成的导电层; 以及在导电间隔物外部的硅衬底和虚拟间隔物中形成的源极和漏极区。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 59. 发明申请
      US20050208744A1 Split gate type nonvolatile semiconductor memory device, and method of fabricating the same 失效
    • Split gate type nonvolatile semiconductor memory device, and method of fabricating the same
    • 分路型非易失性半导体存储器件及其制造方法
    • US20050208744A1
    • 2005-09-22
    • US11083130
    • 2005-03-17
    • Heeseog Jeon , Seung-beom Yoon , Yong-tae Kim , Yong-suk Choi
    • Heeseog Jeon , Seung-beom Yoon , Yong-tae Kim , Yong-suk Choi
    • H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/788 , H01L29/792
    • H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
    • A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.
    • 提供一种分离栅极型非易失性半导体存储器件及其制造分离栅型非易失性半导体存储器件的方法。 在半导体衬底上形成栅绝缘层和浮栅导电层。 掩模层图案形成在浮栅导电层上以限定沿第一方向延伸的第一开口。 具有预定宽度的第一牺牲间隔物形成在对应于掩模层图案的两个侧壁上。 栅极间绝缘层形成在浮栅导电层上。 去除第一牺牲间隔物，并且蚀刻浮栅导电层，直到露出栅极绝缘层。 隧道绝缘层形成在浮栅导电层的露出部分上。 在半导体衬底的表面上形成控制栅导电层。 在控制栅极导电层上形成具有预定宽度的第二牺牲间隔物。 通过蚀刻暴露的控制栅极导电层，在第一开口中形成分裂控制栅极。 蚀刻剩余的掩模层图案和栅极间绝缘层，直到浮栅导电层露出。 蚀刻暴露的浮栅导电层，以在第一开口中形成分离浮栅。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 60. 发明授权
      US06878987B2 Split gate memory device 有权
    • Split gate memory device
    • 分闸存储器件
    • US06878987B2
    • 2005-04-12
    • US10429866
    • 2003-05-06
    • Og-Hyun Lee , Yong Suk Choi
    • Og-Hyun Lee , Yong Suk Choi
    • H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
    • H01L27/11521 , H01L27/115 , H01L29/42324
    • A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.
    • 一种分离栅极存储器件及其制造方法，其中栅极绝缘和多晶硅层顺序地形成在衬底上。 图案化多晶硅层，并且在其部分上形成封盖绝缘层。 形成具有相同底部宽度的一对自对准控制栅极，其中，隧道绝缘层插入在多晶硅层图案和封盖绝缘层的控制栅极和侧壁之间。 选择性地蚀刻隧道绝缘层，图案化多晶硅层和栅极绝缘层以暴露衬底的一部分，从而形成一对浮动栅极。 将离子注入暴露的衬底和邻接控制栅极的衬底的部分，以分别形成公共源极区域和漏极区域。 浮动栅极上的封盖绝缘层可保护隧道绝缘层的尖锐部分免受蚀刻和离子注入期间的侵袭。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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