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1. 发明申请

US20070111451A1 Flash memory device and method of manufacturing the same 审中-公开
标题翻译：闪存装置及其制造方法
公开(公告)号：US20070111451A1
公开(公告)日：2007-05-17
申请号：US11650237
申请日：2007-01-05
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
摘要翻译：提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

2. 发明授权

US07192833B2 Flash memory device and method of manufacturing the same 有权
公开(公告)号：US07192833B2
公开(公告)日：2007-03-20
申请号：US11025279
申请日：2004-12-29
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

3. 发明申请

US20050153502A1 Flash memory device and method of manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US20050153502A1
公开(公告)日：2005-07-14
申请号：US11025279
申请日：2004-12-29
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
摘要翻译：提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

4. 发明授权

US07397079B2 Non-volatile memory device and methods of forming the same 失效
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US07397079B2
公开(公告)日：2008-07-08
申请号：US11245527
申请日：2005-10-07
申请人： Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Jin-Woo Kim
发明人： Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Jin-Woo Kim
IPC分类号： H01L29/76 , H01L29/788 , H01L21/8238
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.
摘要翻译：非易失性存储器件包括设置在衬底上的控制栅电极，其间插入有第一绝缘层，以及设置在通过控制栅电极和第一绝缘层暴露衬底的孔中的浮置栅极。第二绝缘层介于浮置栅极和衬底之间，以及浮置栅极和控制栅极之间。

5. 发明申请

US20060079054A1 Non-volatile memory device and methods of forming the same 失效
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20060079054A1
公开(公告)日：2006-04-13
申请号：US11245527
申请日：2005-10-07
申请人： Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Jin-Woo Kim
发明人： Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Jin-Woo Kim
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.
摘要翻译：非易失性存储器件包括设置在衬底上的控制栅电极，其间插入有第一绝缘层，以及设置在通过控制栅电极和第一绝缘层暴露衬底的孔中的浮置栅极。第二绝缘层介于浮置栅极和衬底之间，以及浮置栅极和控制栅极之间。

6. 发明申请

US20110175153A1 Semiconductor Device Having Transistor with Vertical Gate Electrode and Method of Fabricating the Same 失效
标题翻译：具有具有垂直栅电极的晶体管的半导体器件及其制造方法
公开(公告)号：US20110175153A1
公开(公告)日：2011-07-21
申请号：US13075778
申请日：2011-03-30
申请人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
发明人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L27/105 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.
摘要翻译：半导体器件包括具有垂直栅电极的晶体管。在晶体管结构中，半导体图案具有面向横向的第一和第二侧以及纵向方向上的第三和第四侧。栅极图案被布置成与半导体图案的第一和第二侧相邻。杂质图案直接接触半导体图案的第三面和第四面。栅极绝缘图案插入在栅极图案和半导体图案之间。

7. 发明申请

US20060244042A1 Split gate type nonvolatile memory device and method of fabricating the same 失效
标题翻译：分闸式非易失性存储装置及其制造方法
公开(公告)号：US20060244042A1
公开(公告)日：2006-11-02
申请号：US11413640
申请日：2006-04-28
申请人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
发明人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
摘要翻译：在分闸式非易失存储器件及其制造方法中，辅助层图案设置在半导体衬底的源极区域上。由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

8. 发明申请

US20060199359A1 LOCAL-LENGTH NITRIDE SONOS DEVICE HAVING SELF-ALIGNED ONO STRUCTURE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：具有自对准结构的本地长度NITRIDE SONOS器件及其制造方法
公开(公告)号：US20060199359A1
公开(公告)日：2006-09-07
申请号：US11415466
申请日：2006-05-01
申请人： Hee-Seog Jeon , Seung-Beom Yoon , Yong-Tae Kim
发明人： Hee-Seog Jeon , Seung-Beom Yoon , Yong-Tae Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/4232 , H01L29/792
摘要： In a local-length nitride SONOS device and a method for forming the same, a local-length nitride floating gate structure is provided for mitigating or preventing lateral electron migration in the nitride floating gate. The structure includes a thin gate oxide, which leads to devices having a lower threshold voltage. In addition, the local-length nitride layer is self-aligned, which prevents nitride misalignment, and therefore leads to reduced threshold voltage variation among the devices.
摘要翻译：在本地长度的氮化物SONOS器件及其形成方法中，提供局部长度的氮化物浮栅结构，用于减轻或防止氮化物浮栅中的横向电子迁移。该结构包括薄栅极氧化物，其导致具有较低阈值电压的器件。此外，局部长度的氮化物层是自对准的，这防止氮化物不对准，并且因此导致器件之间的阈值电压变化降低。

9. 发明申请

US20060170034A1 Non-volatile memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060170034A1
公开(公告)日：2006-08-03
申请号：US11339741
申请日：2006-01-25
申请人： Sung-Woo Park , Sung-Taeg Kang , Seung-Beom Yoon , Yong-Tae Kim , Ji-Hoon Park
发明人： Sung-Woo Park , Sung-Taeg Kang , Seung-Beom Yoon , Yong-Tae Kim , Ji-Hoon Park
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L29/40117 , H01L29/792
摘要： Provided are a non-volatile memory device having an improved electric characteristic and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a substrate having a sloped portion formed therein, a first gate electrode pattern having a stacked structure in which an electric charge tunneling layer pattern, an electric charge trapping layer pattern, an electric charge shielding layer pattern, and a storage gate electrode pattern are conformably stacked on the sloped portion, a gate insulating layer pattern extending from a side of the first gate electrode pattern to the substrate, a second gate electrode pattern formed on the gate insulating layer pattern, a first junction region arranged at a side wall of the first gate electrode pattern, which does not face the second gate electrode pattern, and formed in the substrate, and a second junction region arranged at a side wall of the second gate electrode pattern, which does not face the first gate electrode pattern, and formed in the substrate.
摘要翻译：提供了具有改进的电特性的非易失性存储器件和制造非易失性存储器件的方法，其中非易失性存储器件包括其中形成有倾斜部分的衬底，第一栅电极图案具有堆叠其中电荷隧道层图案，电荷捕获层图案，电荷屏蔽层图案和存储栅极电极图案顺应地堆叠在倾斜部分上的结构，从第一部分的侧面延伸的栅极绝缘层图案栅电极图案到基板，形成在栅极绝缘层图案上的第二栅极电极图案，布置在第一栅电极图案的侧壁处的第一接合区域，其不面向第二栅电极图案，并形成在第衬底和布置在第二栅电极图案的侧壁处的第二接合区域，其不面向顶部 t栅电极图案，并形成在基板中。

10. 发明授权

US07936003B2 Semiconductor device having transistor with vertical gate electrode and method of fabricating the same 失效
标题翻译：具有具有垂直栅电极的晶体管的半导体器件及其制造方法
公开(公告)号：US07936003B2
公开(公告)日：2011-05-03
申请号：US11344560
申请日：2006-01-31
申请人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
发明人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
IPC分类号： H01L29/788
CPC分类号： H01L29/785 , H01L27/105 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.
摘要翻译：半导体器件包括具有垂直栅电极的晶体管。在晶体管结构中，半导体图案具有面向横向的第一和第二侧以及纵向方向上的第三和第四侧。栅极图案被布置成与半导体图案的第一和第二侧相邻。杂质图案直接接触半导体图案的第三面和第四面。栅极绝缘图案插入在栅极图案和半导体图案之间。

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