专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08698239B2 Semiconductor devices having asymmetric doped regions and methods of fabricating the same 有权
标题翻译：具有不对称掺杂区域的半导体器件及其制造方法
公开(公告)号：US08698239B2
公开(公告)日：2014-04-15
申请号：US13352194
申请日：2012-01-17
申请人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
发明人： Ji-Do Ryu , Hee-Seog Jeon , Hyun-Khe Yoo , Yong-Suk Choi
IPC分类号： H01L29/66 , H01L29/423 , H01L29/788 , H01L21/28 , H01L27/115 , H01L27/02
CPC分类号： H01L29/42328 , H01L21/28273 , H01L27/0207 , H01L27/11504 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L29/7883
摘要： A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.
摘要翻译：半导体器件包括在衬底中的有源区域，与有源区域交叉并顺序地彼此平行布置的第一至第三栅极结构，位于第一和第二栅极结构之间的有源区域中的第一掺杂区域，并且具有第一水平宽度和第一深度和在第二和第三栅极结构之间的有源区域中的第二掺杂区域，并且具有第二水平宽度和第二深度。第二水平宽度大于第一水平宽度，第二深度比第一深度浅。彼此相邻的第一和第二栅极结构之间的距离小于彼此相邻的第二和第三栅极结构之间的距离。还描述了相关的制造方法。

2. 发明授权

US07599498B2 Apparatus and method for producing 3D sound 有权
标题翻译：用于产生3D声音的装置和方法
公开(公告)号：US07599498B2
公开(公告)日：2009-10-06
申请号：US11175326
申请日：2005-07-07
申请人： Poong-Min Kim , Hyun-Suk Kim , Jin-Wook Kim , Dong-Woo Lee , In-Ho Lee , Yong-Suk Choi , Jeong-Mo Koo , Myung-Cheol Lee , Dong-Sun Shin , Jong-Woo Kim
发明人： Poong-Min Kim , Hyun-Suk Kim , Jin-Wook Kim , Dong-Woo Lee , In-Ho Lee , Yong-Suk Choi , Jeong-Mo Koo , Myung-Cheol Lee , Dong-Sun Shin , Jong-Woo Kim
IPC分类号： H04R5/00
CPC分类号： H04S5/02 , H04R2499/11 , H04S5/00
摘要： Disclosed herein is an apparatus for producing 3D sound. The apparatus includes a determination unit, a mono sound spreading unit, a stereo sound spreading unit, a selection unit, and a 3D sound accelerator. The determination unit receives a source sound file and determines whether the source sound file is mono or stereo. The mono sound spreading unit converts the source sound into pseudo-stereo sound and performs sound spreading on the pseudo-stereo sound, if the source sound is determined to be mono. The stereo sound spreading unit performs sound spreading on the source sound, if the source sound is determined to be stereo. The selection unit receives the output of the mono sound spreading unit or stereo sound spreading unit, and transfers the output to headphones if the headphone reproduction has been selected. The 3D sound accelerator receives the output from the selection unit if speaker reproduction has been selected, removes crosstalk from the output, and transfers the crosstalk-free output to speakers.
摘要翻译：本文公开了一种用于产生3D声音的装置。该装置包括确定单元，单声道扩散单元，立体声扩声单元，选择单元和3D声音加速器。确定单元接收源声音文件并确定源声音文件是单声道还是立体声。如果源声音被确定为单声道，则单声道扩散单元将源声音转换为伪立体声，并对伪立体声进行声音扩展。如果源声音被确定为立体声，则立体声扩散单元对源声音进行声音扩展。选择单元接收单声道扩声单元或立体声声音扩展单元的输出，并且如果已经选择了耳机再现，则将输出传送到耳机。如果选择了扬声器再现，则3D声音加速器从选择单元接收输出，从输出中消除串扰，并将无串扰输出传送给扬声器。

3. 发明申请

US20090189210A1 Semiconductor Flash Memory Device and Method of Fabricating the Same 审中-公开
标题翻译：半导体闪存器件及其制造方法
公开(公告)号：US20090189210A1
公开(公告)日：2009-07-30
申请号：US12416651
申请日：2009-04-01
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Scung-Jin Yang , Ilyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Scung-Jin Yang , Ilyok-Ki Kwon
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/40114 , H01L29/42336
摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.
摘要翻译：半导体闪存器件。闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。栅极绝缘膜介于浮栅电极和半导体衬底之间。控制栅电极设置在浮栅电极上。浮栅电极包括与凹部的倾斜侧相邻的突起。

4. 发明申请

US20080286974A1 Etching solution for multiple layer of copper and molybdenum and etching method using the same 有权
公开(公告)号：US20080286974A1
公开(公告)日：2008-11-20
申请号：US12219446
申请日：2008-07-22
申请人： Seong-Su Kim , Yong-Suk Choi , Gee-Sung Chae , Gyoo-Chul Jo , Oh-Nam Kwon , Kyoung-Mook Lee , Yong-Sup Hwang , Seung-Yong Lee
发明人： Seong-Su Kim , Yong-Suk Choi , Gee-Sung Chae , Gyoo-Chul Jo , Oh-Nam Kwon , Kyoung-Mook Lee , Yong-Sup Hwang , Seung-Yong Lee
IPC分类号： H01L21/311
CPC分类号： C09K13/08 , C23F1/18 , C23F1/26 , H01L21/32134
摘要： An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.

5. 发明授权

US07397079B2 Non-volatile memory device and methods of forming the same 失效
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US07397079B2
公开(公告)日：2008-07-08
申请号：US11245527
申请日：2005-10-07
申请人： Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Jin-Woo Kim
发明人： Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Jin-Woo Kim
IPC分类号： H01L29/76 , H01L29/788 , H01L21/8238
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.
摘要翻译：非易失性存储器件包括设置在衬底上的控制栅电极，其间插入有第一绝缘层，以及设置在通过控制栅电极和第一绝缘层暴露衬底的孔中的浮置栅极。第二绝缘层介于浮置栅极和衬底之间，以及浮置栅极和控制栅极之间。

6. 发明授权

US07320913B2 Methods of forming split-gate non-volatile memory devices 失效
标题翻译：形成分闸非易失性存储器件的方法
公开(公告)号：US07320913B2
公开(公告)日：2008-01-22
申请号：US11368247
申请日：2006-03-03
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

7. 发明申请

US20070170491A1 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070170491A1
公开(公告)日：2007-07-26
申请号：US11698658
申请日：2007-01-26
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Yong-Tae Kim , Seung-Jin Yang , Hyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Yong-Tae Kim , Seung-Jin Yang , Hyok-Ki Kwon
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.
摘要翻译：非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。栅极绝缘层介于控制栅极电极和活性电极之间。在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

8. 发明申请

US20070111451A1 Flash memory device and method of manufacturing the same 审中-公开
标题翻译：闪存装置及其制造方法
公开(公告)号：US20070111451A1
公开(公告)日：2007-05-17
申请号：US11650237
申请日：2007-01-05
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
摘要翻译：提供一种包括隧道介电层，浮栅，层间电介质层和形成在半导体衬底上的至少两个模层的闪存器件及其制造方法。通过顺序地图案化这些层，形成彼此对准的第一模具层图案和浮动栅极层图案。选择性地横向蚀刻第一模具层图案的侧表面的暴露部分，从而在其侧壁中形成具有凹槽的第一模具层第二图案。栅极电介质层形成在与浮动栅层图案相邻的半导体衬底上。具有由第二模层图案中的凹槽确定的宽度的控制栅极形成在栅介质层上。通过去除第一模具层第二图案，在控制门的侧壁上形成间隔物。使用间隔物作为蚀刻掩模来选择性地蚀刻层间电介质层和浮栅层图案的暴露部分，以形成具有由沟槽和间隔物的宽度限定的宽度的浮动栅极。

9. 发明授权

US07192833B2 Flash memory device and method of manufacturing the same 有权
公开(公告)号：US07192833B2
公开(公告)日：2007-03-20
申请号：US11025279
申请日：2004-12-29
申请人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
发明人： Jae-Hwang Kim , Yong-Suk Choi , Seung-Beom Yoon , Yong-Tae Kim , Young-Sam Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328
摘要： A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

10. 发明申请

US20060148172A1 Local sonos-type nonvolatile memory device and method of manufacturing the same 失效
标题翻译：本地声波型非易失性存储器件及其制造方法
公开(公告)号：US20060148172A1
公开(公告)日：2006-07-06
申请号：US11365147
申请日：2006-03-01
申请人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim
发明人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.
摘要翻译：提供本地SONOS型存储器件及其制造方法。该器件包括形成在硅衬底上的栅氧化层; 导电间隔物和虚拟间隔物，其形成在栅极氧化物层上并彼此分离，导电间隔物和虚设间隔物具有面向外的圆形表面; 形成在所述导电间隔物的侧壁上的一对绝缘间隔件和所述虚拟间隔件的彼此面对的侧壁; 在所述一对绝缘间隔物之间以自对准的方式形成的ONO层; 在所述一对绝缘间隔物之间以自对准的方式在所述ONO层上形成的导电层; 以及在导电间隔物外部的硅衬底和虚拟间隔物中形成的源极和漏极区。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式