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1. 发明申请

US20110175153A1 Semiconductor Device Having Transistor with Vertical Gate Electrode and Method of Fabricating the Same 失效
标题翻译：具有具有垂直栅电极的晶体管的半导体器件及其制造方法
公开(公告)号：US20110175153A1
公开(公告)日：2011-07-21
申请号：US13075778
申请日：2011-03-30
申请人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
发明人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L27/105 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.
摘要翻译：半导体器件包括具有垂直栅电极的晶体管。在晶体管结构中，半导体图案具有面向横向的第一和第二侧以及纵向方向上的第三和第四侧。栅极图案被布置成与半导体图案的第一和第二侧相邻。杂质图案直接接触半导体图案的第三面和第四面。栅极绝缘图案插入在栅极图案和半导体图案之间。

2. 发明申请

US20090011589A1 METHOD OF MANUFACTURING SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：分离门型非易失性存储器件的制造方法
公开(公告)号：US20090011589A1
公开(公告)日：2009-01-08
申请号：US12212317
申请日：2008-09-17
申请人： Hee-seog JEON , Seung-beom YOON
发明人： Hee-seog JEON , Seung-beom YOON
IPC分类号： H01L21/3205
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.
摘要翻译：一种制造其中通过自对准工艺形成控制栅极的分离栅型非易失性半导体存储器件的方法。

3. 发明申请

US20080029808A1 NON-VOLATILE MEMORY AND METHOD OF FABRICATING SAME 失效
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20080029808A1
公开(公告)日：2008-02-07
申请号：US11837361
申请日：2007-08-10
申请人： Hee-Seog JEON , Seung-Beom YOON , Jeong-Uk HAN
发明人： Hee-Seog JEON , Seung-Beom YOON , Jeong-Uk HAN
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.
摘要翻译：在一个实施例中，半导体器件包括具有第一结区域和第二结区域的半导体衬底。绝缘浮栅设置在基板上。浮置栅极至少部分地与第一结区重叠。在浮动门上设置绝缘的程序门。程序门具有弯曲的上表面。半导体器件还包括布置在衬底上并与浮动栅极相邻的绝缘擦除栅极。擦除栅极部分地与第二结区重叠。

4. 发明授权

US07285820B2 Flash memory device using semiconductor fin and method thereof 有权
标题翻译：使用半导体鳍片的闪存器件及其方法
公开(公告)号：US07285820B2
公开(公告)日：2007-10-23
申请号：US11216677
申请日：2005-08-31
申请人： Ji-Hoon Park , Seung-Beom Yoon , Jeong-Uk Han , Seong-Gyun Kim , Sung-Taeg Kang , Bo-Young Seo , Sang-Woo Kang , Sung-Woo Park
发明人： Ji-Hoon Park , Seung-Beom Yoon , Jeong-Uk Han , Seong-Gyun Kim , Sung-Taeg Kang , Bo-Young Seo , Sang-Woo Kang , Sung-Woo Park
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/11526 , H01L27/11534 , H01L29/42324 , H01L29/66795 , H01L29/785
摘要： A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.
摘要翻译：根据本发明的闪速存储器件包括半导体鳍片，其包括由不同晶面产生的顶表面和侧表面。闪存器件包括：在半导体鳍片的侧表面和顶表面上形成不同厚度的绝缘层，在绝缘层上依次形成的存储电极，栅极绝缘层和控制栅电极。薄的绝缘层能够通过电荷注入或发射电荷，并且厚的绝缘层增加耦合比。因此，可以提高闪速存储器件的编程或擦除操作的效率。

5. 发明授权

US07238572B2 Method of manufacturing EEPROM cell 失效
标题翻译：制造EEPROM单元的方法
公开(公告)号：US07238572B2
公开(公告)日：2007-07-03
申请号：US11096038
申请日：2005-03-31
申请人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/66825
摘要： A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.
摘要翻译：制造EEPROM单元的方法包括在半导体衬底上生长第一氧化物层; 在所述第一氧化物层上形成第一导电层; 通过图案化所述第一导电层和所述第一氧化物层来形成第一导电图案和隧道氧化物层，所述隧穿氧化物层设置在所述第一导电图案下方; 在所述第一导电图案和所述基板的侧壁上形成栅氧化层，并在所述第一导电图案的两侧上形成第二导电图案; 通过将所述第一导电图案电连接到所述第二导电图案来形成用于浮置栅极的导电层; 在浮栅的导电层上形成耦合氧化物层; 在所述耦合氧化物层上形成第三导电层; 以及通过图案化第三导电层，耦合氧化物层和浮栅的导电层来形成选择晶体管和控制晶体管。选择晶体管与控制晶体管间隔开。形成在隧道氧化物层上的选择晶体管包括由选择栅极，第一耦合氧化物图案和第一浮置栅极形成的栅极堆叠，并且控制晶体管包括由控制栅极形成的栅极堆叠，第二耦合氧化物图案和第二浮栅。

6. 发明申请

US20070063267A1 Self aligned 1 bit local SONOS memory cell 失效
标题翻译：自对准1位本地SONOS存储单元
公开(公告)号：US20070063267A1
公开(公告)日：2007-03-22
申请号：US11600765
申请日：2006-11-17
申请人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
摘要翻译：自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

7. 发明授权

US07190024B2 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
标题翻译：使用热处理制造薄介电层的方法和使用该方法形成的半导体器件
公开(公告)号：US07190024B2
公开(公告)日：2007-03-13
申请号：US11329217
申请日：2006-01-10
申请人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
发明人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L21/0214 , H01L21/3144 , H01L29/513 , H01L29/7881
摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.
摘要翻译：在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

8. 发明授权

US07172938B2 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US07172938B2
公开(公告)日：2007-02-06
申请号：US10987340
申请日：2004-11-12
申请人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
发明人： Yong-suk Choi , Seung-beom Yoon , Seong-gyun Kim , Jae-Hwang Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.
摘要翻译：隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。这些层依次构图。通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

9. 发明授权

US07160777B2 Split-gate nonvolatile memory device and method of manufacturing the same 有权
标题翻译：分离式非易失性存储器件及其制造方法
公开(公告)号：US07160777B2
公开(公告)日：2007-01-09
申请号：US10916670
申请日：2004-08-11
申请人： Yong-Suk Choi , Seung-Beom Yoon
发明人： Yong-Suk Choi , Seung-Beom Yoon
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7886 , H01L29/7887
摘要： Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate insulating layer and separated apart from each other, the floating gate and the dummy pattern having round surfaces that face outward; a pair of insulating spacers, which are formed on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; a control gate formed in a self-aligned manner between the pair of insulating spacers; a tunnel insulating layer interposed between the floating gate and the control gate; and source and drain regions formed in the semiconductor substrate outside the floating gate and the dummy pattern.
摘要翻译：本发明的实施例包括形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上并且彼此分开的间隔物型浮栅和间隔物型图案，浮栅和虚设图案具有面向外的圆形表面; 一对绝缘间隔物，其形成在浮动栅极的侧壁和虚设图案的彼此面对的侧壁上; 在所述一对绝缘间隔件之间以自对准的方式形成的控制栅极; 插入在所述浮动栅极和所述控制栅极之间的隧道绝缘层; 以及在浮置栅极外部的半导体衬底和虚拟图案中形成的源极和漏极区域。

10. 发明授权

US07141473B2 Self-aligned 1 bit local SONOS memory cell and method of fabricating the same 失效
标题翻译：自对准1位本地SONOS存储单元及其制造方法
公开(公告)号：US07141473B2
公开(公告)日：2006-11-28
申请号：US10912046
申请日：2004-08-06
申请人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
发明人： Hee-seog Jeon , Seung-beom Yoon , Yong-tae Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
摘要翻译：自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

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